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Fix BUGBUG in fpgaloader.h, realign fpga\define.v with armsrc\fpgaloader.h
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Alex
parent
12efd96173
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b46e1cb556
1 changed files with 107 additions and 73 deletions
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@ -1,5 +1,4 @@
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//-----------------------------------------------------------------------------
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// Copyright (C) Jonathan Westhues, April 2006
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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@ -32,80 +31,116 @@
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#define FPGA_BITSTREAM_HF_15 4
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/*
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Communication between ARM / FPGA is done inside armsrc/fpgaloader.c (function FpgaSendCommand)
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Send 16 bit command / data pair to FPGA
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Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
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Send 16 bit command / data pair to FPGA with the bit format:
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BUGBUG -- Conflicts with information in ../fpga/define.v
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+------ frame layout circa 2020 ------------------+
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| 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
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+-------------------------------------------------+
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| C C C C M M M M P P P P P P P P | C = FPGA_CMD_SET_CONFREG, M = FPGA_MAJOR_MODE_*, P = FPGA_LF_* or FPGA_HF_* parameter
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| C C C C D D D D D D D D | C = FPGA_CMD_SET_DIVISOR, D = divisor
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| C C C C T T T T T T T T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, T = threshold
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| C C C C E | C = FPGA_CMD_TRACE_ENABLE, E=0 off, E=1 on
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+-------------------------------------------------+
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The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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where
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C is 4bit command
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D is 12bit data
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+------ frame layout current ---------------------+
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| 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
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+-------------------------------------------------+
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| C C C C M M M P P P P P P | C = FPGA_CMD_SET_CONFREG, M = FPGA_MAJOR_MODE_*, P = FPGA_LF_* or FPGA_HF_* parameter
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| C C C C D D D D D D D D | C = FPGA_CMD_SET_DIVISOR, D = divisor
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| C C C C T T T T T T T T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, T = threshold
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| C C C C E | C = FPGA_CMD_TRACE_ENABLE, E=0 off, E=1 on
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+-------------------------------------------------+
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shift_reg receive this 16bit frame
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LF command
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----------
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shift_reg[15:12] == 4bit command
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LF has three commands (FPGA_CMD_SET_CONFREG, FPGA_CMD_SET_DIVISOR, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD)
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Current commands uses only 2bits. We have room for up to 4bits of commands total (7).
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LF data
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-------
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shift_reg[11:0] == 12bit data
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lf data is divided into MAJOR MODES and configuration values.
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The major modes uses 3bits (0,1,2,3,7 | 000, 001, 010, 011, 111)
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000 FPGA_MAJOR_MODE_LF_READER = Act as LF reader (modulate)
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001 FPGA_MAJOR_MODE_LF_EDGE_DETECT = Simulate LF
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010 FPGA_MAJOR_MODE_LF_PASSTHRU = Passthrough mode, CROSS_LO line connected to SSP_DIN. SSP_DOUT logic level controls if we modulate / listening
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011 FPGA_MAJOR_MODE_LF_ADC = refactor hitag2, clear ADC sampling
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111 FPGA_MAJOR_MODE_OFF = turn off sampling.
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Each one of this major modes can have options. Currently these two major modes uses options.
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- FPGA_MAJOR_MODE_LF_READER
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- FPGA_MAJOR_MODE_LF_EDGE_DETECT
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FPGA_MAJOR_MODE_LF_READER
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-------------------------------------
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lf_field = 1bit (FPGA_LF_ADC_READER_FIELD)
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You can send FPGA_CMD_SET_DIVISOR to set with FREQUENCY the fpga should sample at
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divisor = 8bits shift_reg[7:0]
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FPGA_MAJOR_MODE_LF_EDGE_DETECT
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------------------------------------------
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lf_ed_toggle_mode = 1bits
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lf_ed_threshold = 8bits threshold defaults to 127
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You can send FPGA_CMD_SET_EDGE_DETECT_THRESHOLD to set a custom threshold
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lf_ed_threshold = 8bits threshold value.
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conf_word 12bits
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conf_word[7:5] = 3bit major mode.
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conf_word[0] = 1bit lf_field
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conf_word[1] = 1bit lf_ed_toggle_mode
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conf_word[7:0] = 8bit divisor
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conf_word[7:0] = 8bit threshold
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-----+--------- frame layout --------------------
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bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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-----+-------------------------------------------
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cmd | x x x x
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major| x x x
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opt | x x
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divi | x x x x x x x x
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thres| x x x x x x x x
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-----+-------------------------------------------
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*/
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// Definitions for the FPGA commands.
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// BOTH HF / LF
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#define FPGA_CMD_SET_CONFREG (1<<12) // C
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// LF
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#define FPGA_CMD_SET_DIVISOR (2<<12) // C
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#define FPGA_CMD_SET_USER_BYTE1 (3<<12) // C
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// HF
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#define FPGA_CMD_TRACE_ENABLE (2<<12) // C
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// Definitions for the FPGA configuration word.
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// Defining commands, modes and options. This must be aligned to the definitions in fpga/define.v
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#define FPGA_MAJOR_MODE_MASK 0x01C0
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#define FPGA_MINOR_MODE_MASK 0x003F
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// LF
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// Definitions for the FPGA commands.
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#define FPGA_CMD_SET_CONFREG (1<<12)
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#define FPGA_CMD_SET_DIVISOR (2<<12)
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#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD (3<<12)
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#define FPGA_CMD_TRACE_ENABLE (2<<12)
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// Major modes
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#define FPGA_MAJOR_MODE_LF_READER (0<<6)
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#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<6)
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#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<6)
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#define FPGA_MAJOR_MODE_LF_ADC (3<<6)
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// HF
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#define FPGA_MAJOR_MODE_HF_READER (0<<6) // D
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#define FPGA_MAJOR_MODE_HF_SIMULATOR (1<<6) // D
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#define FPGA_MAJOR_MODE_HF_ISO14443A (2<<6) // D
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#define FPGA_MAJOR_MODE_HF_SNIFF (3<<6) // D
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#define FPGA_MAJOR_MODE_HF_ISO18092 (4<<6) // D
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#define FPGA_MAJOR_MODE_HF_GET_TRACE (5<<6) // D
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#define FPGA_MAJOR_MODE_HF_FSK_READER (6<<6) // D
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// BOTH HF / LF
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#define FPGA_MAJOR_MODE_OFF (7<<6) // D
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#define FPGA_MAJOR_MODE_HF_READER (0<<6)
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#define FPGA_MAJOR_MODE_HF_SIMULATOR (1<<6)
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#define FPGA_MAJOR_MODE_HF_ISO14443A (2<<6)
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#define FPGA_MAJOR_MODE_HF_SNIFF (3<<6)
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#define FPGA_MAJOR_MODE_HF_ISO18092 (4<<6)
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#define FPGA_MAJOR_MODE_HF_GET_TRACE (5<<6)
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#define FPGA_MAJOR_MODE_OFF (7<<6)
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// Options for LF_READER
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#define FPGA_LF_ADC_READER_FIELD 0x1
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#define FPGA_LF_ADC_READER_FIELD ( 1 )
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// Options for LF_EDGE_DETECT
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#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD FPGA_CMD_SET_USER_BYTE1
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#define FPGA_LF_EDGE_DETECT_READER_FIELD 0x1
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#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 0x2
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#define FPGA_LF_EDGE_DETECT_READER_FIELD ( 1 )
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#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE ( 2 )
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// Options for the HF reader
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#define FPGA_HF_READER_MODE_RECEIVE_IQ (0<<0)
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#define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE (1<<0)
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#define FPGA_HF_READER_MODE_RECEIVE_PHASE (2<<0)
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#define FPGA_HF_READER_MODE_SEND_FULL_MOD (3<<0)
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#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD (4<<0)
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#define FPGA_HF_READER_MODE_SNIFF_IQ (5<<0)
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#define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE (6<<0)
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#define FPGA_HF_READER_MODE_SNIFF_PHASE (7<<0)
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#define FPGA_HF_READER_MODE_SEND_JAM (8<<0)
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#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4 (9<<0)
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// Options for the generic HF reader
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#define FPGA_HF_READER_MODE_RECEIVE_IQ ( 0 )
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#define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE ( 1 )
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#define FPGA_HF_READER_MODE_RECEIVE_PHASE ( 2 )
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#define FPGA_HF_READER_MODE_SEND_FULL_MOD ( 3 )
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#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD ( 4 )
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#define FPGA_HF_READER_MODE_SNIFF_IQ ( 5 )
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#define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE ( 6 )
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#define FPGA_HF_READER_MODE_SNIFF_PHASE ( 7 )
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#define FPGA_HF_READER_MODE_SEND_JAM ( 8 )
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#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4 ( 9 )
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#define FPGA_HF_READER_SUBCARRIER_848_KHZ (0<<4)
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#define FPGA_HF_READER_SUBCARRIER_424_KHZ (1<<4)
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@ -113,24 +148,23 @@ thres| x x x x x x x x
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#define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ (3<<4)
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// Options for the HF simulated tag, how to modulate
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#define FPGA_HF_SIMULATOR_NO_MODULATION 0x0 // 0000
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#define FPGA_HF_SIMULATOR_MODULATE_BPSK 0x1 // 0001
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#define FPGA_HF_SIMULATOR_MODULATE_212K 0x2 // 0010
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#define FPGA_HF_SIMULATOR_MODULATE_424K 0x4 // 0100
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#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5 // 0101
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// no 848K
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#define FPGA_HF_SIMULATOR_NO_MODULATION ( 0 )
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#define FPGA_HF_SIMULATOR_MODULATE_BPSK ( 1 )
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#define FPGA_HF_SIMULATOR_MODULATE_212K ( 2 )
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#define FPGA_HF_SIMULATOR_MODULATE_424K ( 4 )
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#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT ( 5 )
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// Options for ISO14443A
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#define FPGA_HF_ISO14443A_SNIFFER 0x0
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#define FPGA_HF_ISO14443A_TAGSIM_LISTEN 0x1
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#define FPGA_HF_ISO14443A_TAGSIM_MOD 0x2
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#define FPGA_HF_ISO14443A_READER_LISTEN 0x3
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#define FPGA_HF_ISO14443A_READER_MOD 0x4
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#define FPGA_HF_ISO14443A_SNIFFER ( 0 )
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#define FPGA_HF_ISO14443A_TAGSIM_LISTEN ( 1 )
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#define FPGA_HF_ISO14443A_TAGSIM_MOD ( 2 )
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#define FPGA_HF_ISO14443A_READER_LISTEN ( 3 )
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#define FPGA_HF_ISO14443A_READER_MOD ( 4 )
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//options for Felica.
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#define FPGA_HF_ISO18092_FLAG_NOMOD 0x1 // 0001 disable modulation module
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#define FPGA_HF_ISO18092_FLAG_424K 0x2 // 0010 should enable 414k mode (untested). No autodetect
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#define FPGA_HF_ISO18092_FLAG_READER 0x4 // 0100 enables antenna power, to act as a reader instead of tag
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// Options for ISO18092 / Felica
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#define FPGA_HF_ISO18092_FLAG_NOMOD ( 1 ) // 0001 disable modulation module
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#define FPGA_HF_ISO18092_FLAG_424K ( 2 ) // 0010 should enable 414k mode (untested). No autodetect
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#define FPGA_HF_ISO18092_FLAG_READER ( 4 ) // 0100 enables antenna power, to act as a reader instead of tag
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void FpgaSendCommand(uint16_t cmd, uint16_t v);
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void FpgaWriteConfWord(uint16_t v);
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