From b304adeecabaceda477ebf019b35437f46f5f78a Mon Sep 17 00:00:00 2001 From: iceman1001 Date: Sat, 22 Feb 2020 13:16:04 +0100 Subject: [PATCH] hitag, determine adc levels to get better demodulation --- armsrc/lfadc.c | 39 +++++++++++++++++++++++++++++---------- armsrc/lfadc.h | 1 + 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/armsrc/lfadc.c b/armsrc/lfadc.c index 04f293e1d..6b0eb930a 100644 --- a/armsrc/lfadc.c +++ b/armsrc/lfadc.c @@ -10,6 +10,7 @@ #include "lfsampling.h" #include "fpgaloader.h" #include "ticks.h" +#include "dbprint.h" // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK) // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz @@ -46,13 +47,28 @@ bool lf_test_periods(size_t expected, size_t count) { // Low frequency (LF) adc passthrough functionality ////////////////////////////////////////////////////////////////////////////// uint8_t previous_adc_val = 0; +uint8_t adc_avg = 0; + +void lf_sample_mean(void) { + uint8_t periods = 0; + uint32_t adc_sum = 0; + while (periods < 32) { + if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { + adc_sum += AT91C_BASE_SSC->SSC_RHR; + periods++; + } + } + // division by 32 + adc_avg = adc_sum >> 5; + + if (DBGLEVEL >= DBG_EXTENDED) + Dbprintf("LF ADC average %u", adc_avg); +} size_t lf_count_edge_periods_ex(size_t max, bool wait, bool detect_gap) { size_t periods = 0; volatile uint8_t adc_val; - //uint8_t avg_peak = 140, avg_through = 96; - // 140 - 127 - 114 - uint8_t avg_peak = 140, avg_through = 106; + uint8_t avg_peak = adc_avg + 3, avg_through = adc_avg - 3; int16_t checked = 0; while (!BUTTON_PRESS()) { @@ -98,8 +114,8 @@ size_t lf_count_edge_periods_ex(size_t max, bool wait, bool detect_gap) { } } } - previous_adc_val = adc_val; + if (periods >= max) return 0; } } @@ -131,8 +147,9 @@ void lf_reset_counter() { bool lf_get_tag_modulation() { return (rising_edge == false); } + bool lf_get_reader_modulation() { - return rising_edge; + return rising_edge; } void lf_wait_periods(size_t periods) { @@ -147,7 +164,7 @@ void lf_init(bool reader, bool simulate) { FpgaDownloadAndGo(FPGA_BITSTREAM_LF); - FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz + FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); if (reader) { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); } else { @@ -168,8 +185,8 @@ void lf_init(bool reader, bool simulate) { // When in reader mode, give the field a bit of time to settle. // 313T0 = 313 * 8us = 2504us = 2.5ms Hitag2 tags needs to be fully powered. if (reader) { - // 50 ms - SpinDelay(50); + // 10 ms + SpinDelay(10); } // Steal this pin from the SSP (SPI communication channel with fpga) and use it to control the modulation @@ -195,7 +212,7 @@ void lf_init(bool reader, bool simulate) { AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // Prepare data trace - uint32_t bufsize = 20000; + uint32_t bufsize = 10000; // use malloc if (logging) initSampleBufferEx(&bufsize, true); @@ -203,6 +220,8 @@ void lf_init(bool reader, bool simulate) { sample_config *sc = getSamplingConfig(); sc->decimation = 1; sc->averaging = 0; + + lf_sample_mean(); } void lf_finalize() { @@ -275,7 +294,7 @@ static void lf_manchester_send_bit(uint8_t bit) { lf_modulation(bit != 0); lf_wait_periods(16); lf_modulation(bit == 0); - lf_wait_periods(16); + lf_wait_periods(32); } // simulation diff --git a/armsrc/lfadc.h b/armsrc/lfadc.h index 8c33aa778..09e5762c6 100644 --- a/armsrc/lfadc.h +++ b/armsrc/lfadc.h @@ -17,6 +17,7 @@ extern bool logging; +void lf_sample_mean(void); bool lf_test_periods(size_t expected, size_t count); size_t lf_count_edge_periods(size_t max); size_t lf_detect_gap(size_t max);