From ad73af95c215f58122a7093b12138d99d123684b Mon Sep 17 00:00:00 2001 From: iceman1001 Date: Tue, 13 Feb 2018 11:41:23 +0100 Subject: [PATCH] ADD: beginning to add SPI to access flash memory. --- armsrc/fpgaloader.c | 25 ++++++++++++++++++++++++- include/at91sam7s512.h | 1 + include/config_gpio.h | 1 + include/proxmark3.h | 2 ++ 4 files changed, 28 insertions(+), 1 deletion(-) diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c index 9e1ee499a..ebf7d0dfc 100644 --- a/armsrc/fpgaloader.c +++ b/armsrc/fpgaloader.c @@ -34,6 +34,7 @@ static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0 // May also be used to write to other SPI attached devices like an LCD //----------------------------------------------------------------------------- void SetupSpi(int mode) { + // PA1 -> SPI_NCS3 chip select (MEM) // PA10 -> SPI_NCS2 chip select (LCD) // PA11 -> SPI_NCS0 chip select (FPGA) // PA12 -> SPI_MISO Master-In Slave-Out @@ -44,6 +45,7 @@ void SetupSpi(int mode) { AT91C_BASE_PIOA->PIO_PDR = GPIO_NCS0 | GPIO_NCS2 | + GPIO_NCS3 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK; @@ -54,7 +56,9 @@ void SetupSpi(int mode) { GPIO_MOSI | GPIO_SPCK; - AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2; + AT91C_BASE_PIOA->PIO_BSR = + GPIO_NCS2 | + GPIO_NCS3; //enable the SPI Peripheral clock AT91C_BASE_PMC->PMC_PCER = (1<SPI_MR = + ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods) + ( 1 << 16) | // Peripheral Chip Select (selects MEM SPI_NCS3 or PA1) ---> IS THIS CORRECT Chipset pin PA1? + ( 0 << 7) | // Local Loopback Disabled + ( 1 << 4) | // Mode Fault Detection disabled + ( 0 << 2) | // Chip selects connected directly to peripheral + ( 0 << 1) | // Fixed Peripheral Select + ( 1 << 0); // Master Mode + AT91C_BASE_SPI->SPI_CSR[2] = + ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods) + ( 1 << 16) | // Delay Before SPCK (1 MCK period) + ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud + ( 8 << 4) | // Bits per Transfer (16 bits) ---> TRANSFER RATE CORRECT? + ( 0 << 3) | // Chip Select inactive after transfer + ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge + ( 0 << 0); // Clock Polarity inactive state is logic 0 + + break; default: // Disable SPI AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS; break; diff --git a/include/at91sam7s512.h b/include/at91sam7s512.h index 47c79ee41..67f308eaa 100644 --- a/include/at91sam7s512.h +++ b/include/at91sam7s512.h @@ -2111,6 +2111,7 @@ typedef struct _AT91S_UDP { #define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 #define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 #define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PA1_NPCS3 (AT91C_PIO_PA1) // SPI Peripheral Chip Select 3 #define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 #define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 #define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock diff --git a/include/config_gpio.h b/include/config_gpio.h index 5307c220f..b61a27561 100644 --- a/include/config_gpio.h +++ b/include/config_gpio.h @@ -19,6 +19,7 @@ #define GPIO_LRST AT91C_PIO_PA7 #define GPIO_LED_B AT91C_PIO_PA8 #define GPIO_LED_C AT91C_PIO_PA9 +#define GPIO_NCS3 AT91C_PA1_NPCS3 #define GPIO_NCS2 AT91C_PA10_NPCS2 #define GPIO_NCS0 AT91C_PA11_NPCS0 #define GPIO_MISO AT91C_PA12_MISO diff --git a/include/proxmark3.h b/include/proxmark3.h index 7e1c9e5ec..fc0001c86 100644 --- a/include/proxmark3.h +++ b/include/proxmark3.h @@ -59,8 +59,10 @@ #define SETBIT(x, y) (y) ? (HIGH(x)):(LOW(x)) #define INVBIT(x) SETBIT((x), !(GETBIT(x))) +// Setup for SPI current modes #define SPI_FPGA_MODE 0 #define SPI_LCD_MODE 1 +#define SPI_MEM_MODE 2 #ifndef COTAG_BITS #define COTAG_BITS 264