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FIX: lf t55xx detect works better with adjusted timings

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CHG: applied fpga_off patch.
This commit is contained in:
Chris 2018-09-10 21:45:00 +02:00
commit 9ee550af45
1 changed files with 26 additions and 21 deletions
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47
armsrc/lfops.c
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@ -26,10 +26,10 @@
# define OPEN_COIL() HIGH(GPIO_SSC_DOUT) # define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
#endif #endif
#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc) #define START_GAP 28*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc) #define WRITE_GAP 17*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc) #define WRITE_0 15*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
#define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550 #define WRITE_1 47*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
#define READ_GAP 15*8 #define READ_GAP 15*8
// VALUES TAKEN FROM EM4x function: SendForward // VALUES TAKEN FROM EM4x function: SendForward
@ -68,7 +68,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint
// Make sure the tag is reset // Make sure the tag is reset
FpgaDownloadAndGo(FPGA_BITSTREAM_LF); FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
WaitMS(500); WaitMS(500);
// clear read buffer // clear read buffer
@ -109,7 +109,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint
if (command[counter] == '0') { if (command[counter] == '0') {
// if field already off leave alone (affects timing otherwise) // if field already off leave alone (affects timing otherwise)
if (off == false) { if (off == false) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
LED_D_OFF(); LED_D_OFF();
off = true; off = true;
} }
@ -136,7 +136,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint
TurnReadLFOn(period_1); TurnReadLFOn(period_1);
LED_D_OFF(); LED_D_OFF();
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
WaitUS(delay_off); WaitUS(delay_off);
} }
@ -1269,7 +1269,7 @@ void T55xxWriteBit(int bit) {
TurnReadLFOn(WRITE_0); TurnReadLFOn(WRITE_0);
else else
TurnReadLFOn(WRITE_1); TurnReadLFOn(WRITE_1);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
WaitUS(WRITE_GAP); WaitUS(WRITE_GAP);
} }
@ -1279,14 +1279,15 @@ void T55xxResetRead(void) {
//clear buffer now so it does not interfere with timing later //clear buffer now so it does not interfere with timing later
BigBuf_Clear_keep_EM(); BigBuf_Clear_keep_EM();
StartTicks();
// Set up FPGA, 125kHz // Set up FPGA, 125kHz
LFSetupFPGAForADC(95, true); LFSetupFPGAForADC(95, true);
StartTicks();
// make sure tag is fully powered up... // make sure tag is fully powered up...
WaitMS(5); WaitMS(6);
// Trigger T55x7 in mode. // Trigger T55x7 in mode.
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
WaitUS(START_GAP); WaitUS(START_GAP);
// reset tag - op code 00 // reset tag - op code 00
@ -1312,13 +1313,15 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
bool testMode = arg & 0x4; bool testMode = arg & 0x4;
uint32_t i = 0; uint32_t i = 0;
StartTicks();
// Set up FPGA, 125kHz // Set up FPGA, 125kHz
LFSetupFPGAForADC(95, true); LFSetupFPGAForADC(95, true);
StartTicks();
// make sure tag is fully powered up... // make sure tag is fully powered up...
WaitMS(5); WaitMS(6);
// Trigger T55x7 in mode. // Trigger T55x7 in mode.
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
WaitUS(START_GAP); WaitUS(START_GAP);
if (testMode) Dbprintf("TestMODE"); if (testMode) Dbprintf("TestMODE");
@ -1396,13 +1399,14 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
//make sure block is at max 7 //make sure block is at max 7
Block &= 0x7; Block &= 0x7;
StartTicks();
// Set up FPGA, 125kHz to power up the tag // Set up FPGA, 125kHz to power up the tag
LFSetupFPGAForADC(95, true); LFSetupFPGAForADC(95, true);
StartTicks();
// make sure tag is fully powered up... // make sure tag is fully powered up...
WaitMS(5); WaitMS(6);
// Trigger T55x7 Direct Access Mode with start gap // Trigger T55x7 Direct Access Mode with start gap
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
WaitUS(START_GAP); WaitUS(START_GAP);
// Opcode 1[page] // Opcode 1[page]
@ -1441,14 +1445,15 @@ void T55xxWakeUp(uint32_t Pwd){
LED_B_ON(); LED_B_ON();
uint32_t i = 0; uint32_t i = 0;
StartTicks();
// Set up FPGA, 125kHz // Set up FPGA, 125kHz
LFSetupFPGAForADC(95, true); LFSetupFPGAForADC(95, true);
StartTicks();
// make sure tag is fully powered up... // make sure tag is fully powered up...
WaitMS(5); WaitMS(6);
// Trigger T55x7 Direct Access Mode // Trigger T55x7 Direct Access Mode
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
WaitUS(START_GAP); WaitUS(START_GAP);
// Opcode 10 // Opcode 10
@ -1888,7 +1893,7 @@ This triggers a COTAG tag to response
*/ */
void Cotag(uint32_t arg0) { void Cotag(uint32_t arg0) {
#ifndef OFF #ifndef OFF
# define OFF { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); } # define OFF { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF); WaitUS(2035); }
#endif #endif
#ifndef ON #ifndef ON
# define ON(x) { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); } # define ON(x) { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); }