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Merge pull request #535 from RfidResearchGroup/hitag

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Hitag
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Iceman 2020-01-22 17:49:40 +01:00 • committed by GitHub
commit 9b1aa02c77
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2 changed files with 10 additions and 4 deletions
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3
Makefile.host
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@ -8,6 +8,9 @@ endif
ifeq ($(DEFSBEENHERE),) ifeq ($(DEFSBEENHERE),)
-include ../../Makefile.defs -include ../../Makefile.defs
endif endif
ifeq ($(DEFSBEENHERE),)
-include ../../../Makefile.defs
endif
ifeq ($(DEFSBEENHERE),) ifeq ($(DEFSBEENHERE),)
$(error Can't find Makefile.defs) $(error Can't find Makefile.defs)
endif endif

11
armsrc/lfsampling.c
View file

@ -200,7 +200,7 @@ void logSample(uint8_t sample, uint8_t decimation, uint8_t bits_per_sample, bool
* 0 or 95 ==> 125 kHz * 0 or 95 ==> 125 kHz
* *
**/ **/
void LFSetupFPGAForADC(int divisor, bool lf_field) { void LFSetupFPGAForADC(int divisor, bool reader_field) {
FpgaDownloadAndGo(FPGA_BITSTREAM_LF); FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
if ((divisor == 1) || (divisor < 0) || (divisor > 255)) if ((divisor == 1) || (divisor < 0) || (divisor > 255))
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); //~134kHz FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); //~134kHz
@ -209,14 +209,17 @@ void LFSetupFPGAForADC(int divisor, bool lf_field) {
else else
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0)); FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | (reader_field ? FPGA_LF_ADC_READER_FIELD : 0));
// Connect the A/D to the peak-detected low-frequency path. // Connect the A/D to the peak-detected low-frequency path.
SetAdcMuxFor(GPIO_MUXSEL_LOPKD); SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// 50ms for the resonant antenna to settle. // 50ms for the resonant antenna to settle.
if (reader_field)
SpinDelay(50); SpinDelay(50);
// Now set up the SSC to get the ADC samples that are now streaming at us. // Now set up the SSC to get the ADC samples that are now streaming at us.
FpgaSetupSsc(); FpgaSetupSsc();
// start a 1.5ticks is 1us // start a 1.5ticks is 1us
StartTicks(); StartTicks();
} }
@ -333,11 +336,11 @@ uint32_t DoPartialAcquisition(int trigger_threshold, bool verbose, uint32_t samp
return DoAcquisition(1, 8, 0, trigger_threshold, verbose, sample_size, cancel_after, 0); return DoAcquisition(1, 8, 0, trigger_threshold, verbose, sample_size, cancel_after, 0);
} }
uint32_t ReadLF(bool activeField, bool verbose, uint32_t sample_size) { uint32_t ReadLF(bool reader_field, bool verbose, uint32_t sample_size) {
if (verbose) if (verbose)
printConfig(); printConfig();
LFSetupFPGAForADC(config.divisor, activeField); LFSetupFPGAForADC(config.divisor, reader_field);
uint32_t ret = DoAcquisition_config(verbose, sample_size); uint32_t ret = DoAcquisition_config(verbose, sample_size);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
return ret; return ret;