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ADD: @pwpivi 's latest fixes for bigbuff
ADD: @marshmellow 14b changes. fix: fixes to the timing inside iso14443b.c sniff/sending. Between TX & RX there should be a 151us pause.
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12 changed files with 153 additions and 143 deletions
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@ -321,9 +321,6 @@ static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
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//-----------------------------------------------------------------------------
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void SimulateIso14443bTag(void)
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{
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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BigBuf_free();
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// the only commands we understand is REQB, AFI=0, Select All, N=0:
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static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
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// ... and REQB, AFI=0, Normal Request, N=0:
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@ -337,22 +334,26 @@ void SimulateIso14443bTag(void)
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0x00, 0x21, 0x85, 0x5e, 0xd7
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};
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uint8_t parity[MAX_PARITY_SIZE];
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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clear_trace();
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set_tracing(TRUE);
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const uint8_t *resp;
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uint8_t *respCode;
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uint16_t respLen, respCodeLen;
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// allocate command receive buffer
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BigBuf_free();
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uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
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uint16_t len;
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uint16_t cmdsRecvd = 0;
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// allocate command receive buffer
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uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
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// prepare the (only one) tag answer:
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CodeIso14443bAsTag(response1, sizeof(response1));
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uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
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memcpy(resp1Code, ToSend, ToSendMax);
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uint16_t resp1CodeLen = ToSendMax;
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@ -371,7 +372,6 @@ void SimulateIso14443bTag(void)
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}
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if (tracing) {
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uint8_t parity[MAX_PARITY_SIZE];
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LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
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}
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@ -444,12 +444,9 @@ void SimulateIso14443bTag(void)
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}
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// trace the response:
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if (tracing) {
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uint8_t parity[MAX_PARITY_SIZE];
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LogTrace(resp, respLen, 0, 0, parity, FALSE);
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}
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if (tracing) LogTrace(resp, respLen, 0, 0, parity, FALSE);
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}
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//FpgaDisableSscDma();
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}
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//=============================================================================
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@ -728,13 +725,13 @@ static void GetSamplesFor14443bDemod(int n, bool quiet)
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BigBuf_free();
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// The response (tag -> reader) that we're receiving.
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uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
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uint8_t *resp = BigBuf_malloc(MAX_FRAME_SIZE);
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// The DMA buffer, used to stream samples from the FPGA
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int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
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// Set up the demodulator for tag -> reader responses.
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DemodInit(receivedResponse);
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DemodInit(resp);
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// Setup and start DMA.
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FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
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@ -746,6 +743,7 @@ static void GetSamplesFor14443bDemod(int n, bool quiet)
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LED_D_ON();
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// And put the FPGA in the appropriate mode
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
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SpinDelayUs(151); // T0 time between reader send, tag answer. 151us.
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for(;;) {
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int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
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@ -922,7 +920,8 @@ static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
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void ReadSTMemoryIso14443b(uint32_t dwLast)
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{
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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BigBuf_free();
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clear_trace();
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set_tracing(TRUE);
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@ -932,6 +931,8 @@ void ReadSTMemoryIso14443b(uint32_t dwLast)
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// confusing things will happen if we don't reset them between reads.
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LED_D_OFF();
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelay(200);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaSetupSsc();
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@ -1169,8 +1170,8 @@ void RAMFUNC SnoopIso14443b(void)
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//Use samples as a time measurement
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if(tracing)
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{
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uint8_t parity[MAX_PARITY_SIZE];
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LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
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//uint8_t parity[MAX_PARITY_SIZE];
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LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
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}
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triggered = TRUE;
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@ -1213,9 +1214,12 @@ void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, u
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaSetupSsc();
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set_tracing(TRUE);
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CodeAndTransmit14443bAsReader(data, datalen);
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if ( datalen == 0 && recv == 0 && powerfield == 0){
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clear_trace();
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} else {
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set_tracing(TRUE);
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CodeAndTransmit14443bAsReader(data, datalen);
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}
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if(recv) {
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GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
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@ -1227,5 +1231,7 @@ void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, u
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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}
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FpgaDisableSscDma();
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}
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