diff --git a/fpga/Makefile b/fpga/Makefile
index 1acec97c2..2411ab7e8 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -74,7 +74,11 @@ TARGET3_OPTIONS = -define \{WITH_HF0 WITH_HF1 WITH_HF3 WITH_HF5 WITH_HF_15 WITH_
 # RDV40/Generic - Enable all HF modules except ISO14443
 TARGET4_OPTIONS = -define \{WITH_HF0 WITH_HF1 WITH_HF3 WITH_HF4 WITH_HF5\}
 # ICOPYX
-TARGET5_OPTIONS = -define {PM3ICOPYX} -rtlview Yes
+TARGET5_OPTIONS = $(TARGET1_OPTIONS)
+TARGET6_OPTIONS = $(TARGET1_OPTIONS)
+TARGET7_OPTIONS = $(TARGET1_OPTIONS)
+TARGET8_OPTIONS = $(TARGET1_OPTIONS)
+TARGET9_OPTIONS = $(TARGET1_OPTIONS)
 
 # Here we list the target names
 TARGET1_NAME = fpga_pm3_lf
@@ -82,6 +86,10 @@ TARGET2_NAME = fpga_pm3_hf
 TARGET3_NAME = fpga_pm3_hf_15
 TARGET4_NAME = fpga_pm3_felica
 TARGET5_NAME = fpga_icopyx_hf
+TARGET6_NAME = fpga_pm3_ult_lf
+TARGET7_NAME = fpga_pm3_ult_hf
+TARGET8_NAME = fpga_pm3_ult_hf_15
+TARGET9_NAME = fpga_pm3_ult_felica
 
 # Targets can be compiled for different FPGA flavours
 TARGET1_FPGA = xc2s30-5-vq100
@@ -89,6 +97,10 @@ TARGET2_FPGA = $(TARGET1_FPGA)
 TARGET3_FPGA = $(TARGET1_FPGA)
 TARGET4_FPGA = $(TARGET1_FPGA)
 TARGET5_FPGA = xc3s100e-4-vq100
+TARGET6_FPGA = xc2s50-5-tq144
+TARGET7_FPGA = $(TARGET6_FPGA)
+TARGET8_FPGA = $(TARGET6_FPGA)
+TARGET9_FPGA = $(TARGET6_FPGA)
 
 # Assemble the final XST options for each target
 TARGET1_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA)  -p $(TARGET1_FPGA) -ofn $(TARGET1_NAME) $(TARGET1_OPTIONS)
@@ -96,6 +108,10 @@ TARGET2_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA)  -p $(TARGET2_FPGA) -ofn $(
 TARGET3_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA)  -p $(TARGET3_FPGA) -ofn $(TARGET3_NAME) $(TARGET3_OPTIONS)
 TARGET4_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA)  -p $(TARGET4_FPGA) -ofn $(TARGET4_NAME) $(TARGET4_OPTIONS)
 TARGET5_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_SPEED) -p $(TARGET5_FPGA) -ofn $(TARGET5_NAME) $(TARGET5_OPTIONS)
+TARGET6_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_SPEED) -p $(TARGET6_FPGA) -ofn $(TARGET6_NAME) $(TARGET6_OPTIONS)
+TARGET7_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_SPEED) -p $(TARGET7_FPGA) -ofn $(TARGET7_NAME) $(TARGET7_OPTIONS)
+TARGET8_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_SPEED) -p $(TARGET8_FPGA) -ofn $(TARGET8_NAME) $(TARGET8_OPTIONS)
+TARGET9_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_SPEED) -p $(TARGET9_FPGA) -ofn $(TARGET9_NAME) $(TARGET9_OPTIONS)
 
 # these files are common for all targets
 TARGET_COMMON_FILES  = define.v
@@ -121,14 +137,18 @@ TARGET2_FILES = $(TARGET1_FILES)
 TARGET3_FILES = $(TARGET1_FILES)
 TARGET4_FILES = $(TARGET1_FILES)
 TARGET5_FILES = $(TARGET_COMMON_FILES) mux2_onein.v mux2_oneout.v fpga_icopyx_hf.v fpga_icopyx_lf.v fpga_icopyx_top.v
+TARGET6_FILES = $(TARGET1_FILES)
+TARGET7_FILES = $(TARGET1_FILES)
+TARGET8_FILES = $(TARGET1_FILES)
+TARGET9_FILES = $(TARGET1_FILES)
 
 # List of all valid target FPGA images to build
-TARGETS = $(TARGET1_NAME) $(TARGET2_NAME) $(TARGET3_NAME) $(TARGET4_NAME) $(TARGET5_NAME)
+TARGETS = $(TARGET1_NAME) $(TARGET2_NAME) $(TARGET3_NAME) $(TARGET4_NAME) $(TARGET5_NAME) $(TARGET6_NAME) $(TARGET7_NAME) $(TARGET8_NAME) $(TARGET9_NAME)
 
 #  Verbosity type for ISE tools ise|xflow|silent
 VERBOSITY = -intstyle silent
 # Echo (Q=) or not echo (Q=@) build commands to the terminal
-Q=@
+Q=
 
 # Pass the custom variables to the lower make rules
 $(TARGET1_NAME).bit: TARGET_FPGA = $(TARGET1_FPGA)
@@ -151,6 +171,22 @@ $(TARGET5_NAME).bit: TARGET_FPGA = $(TARGET5_FPGA)
 $(TARGET5_NAME).bit: TARGET_FILES = $(TARGET5_FILES)
 $(TARGET5_NAME).bit: TARGET_XST_OPTS = $(TARGET5_XST_OPTS)
 
+$(TARGET6_NAME).bit: TARGET_FPGA = $(TARGET6_FPGA)
+$(TARGET6_NAME).bit: TARGET_FILES = $(TARGET6_FILES)
+$(TARGET6_NAME).bit: TARGET_XST_OPTS = $(TARGET6_XST_OPTS)
+
+$(TARGET7_NAME).bit: TARGET_FPGA = $(TARGET7_FPGA)
+$(TARGET7_NAME).bit: TARGET_FILES = $(TARGET7_FILES)
+$(TARGET7_NAME).bit: TARGET_XST_OPTS = $(TARGET7_XST_OPTS)
+
+$(TARGET8_NAME).bit: TARGET_FPGA = $(TARGET8_FPGA)
+$(TARGET8_NAME).bit: TARGET_FILES = $(TARGET8_FILES)
+$(TARGET8_NAME).bit: TARGET_XST_OPTS = $(TARGET8_XST_OPTS)
+
+$(TARGET9_NAME).bit: TARGET_FPGA = $(TARGET9_FPGA)
+$(TARGET9_NAME).bit: TARGET_FILES = $(TARGET9_FILES)
+$(TARGET9_NAME).bit: TARGET_XST_OPTS = $(TARGET9_XST_OPTS)
+
 $(TARGETS):
 	$(Q)$(MKDIR) $(PREFIX)build_$@
 	$(Q)$(MAKE) -C $(PREFIX)build_$@ -f ../Makefile $(notdir $@).bit
@@ -188,7 +224,7 @@ work:
 	$(Q)$(RM) $@ $*.drc $*.rbt
 	$(info [=] BITGEN $@)
 	$(Q)$(XILINX_TOOLS_PREFIX)bitgen $(VERBOSITY) -w $* $@
-	python3 ../strip_date_time_from_binary.py $@ || true
+	$(Q)python3 ../strip_date_time_from_binary.py $@ || true
 	$(Q)$(CP) $@ ..
 
 # Build all targets
diff --git a/fpga/fpga_icopyx_hf.bit b/fpga/fpga_icopyx_hf.bit
index a7824dd74..6198fa35f 100644
Binary files a/fpga/fpga_icopyx_hf.bit and b/fpga/fpga_icopyx_hf.bit differ
diff --git a/fpga/fpga_pm3_ult_felica.bit b/fpga/fpga_pm3_ult_felica.bit
new file mode 100644
index 000000000..31bff7c05
Binary files /dev/null and b/fpga/fpga_pm3_ult_felica.bit differ
diff --git a/fpga/fpga_pm3_ult_hf.bit b/fpga/fpga_pm3_ult_hf.bit
new file mode 100644
index 000000000..4effbe83a
Binary files /dev/null and b/fpga/fpga_pm3_ult_hf.bit differ
diff --git a/fpga/fpga_pm3_ult_hf_15.bit b/fpga/fpga_pm3_ult_hf_15.bit
new file mode 100644
index 000000000..deff00d73
Binary files /dev/null and b/fpga/fpga_pm3_ult_hf_15.bit differ
diff --git a/fpga/fpga_pm3_ult_lf.bit b/fpga/fpga_pm3_ult_lf.bit
new file mode 100644
index 000000000..74fbb661b
Binary files /dev/null and b/fpga/fpga_pm3_ult_lf.bit differ