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chg: adjustments
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parent
535c92fee5
commit
8eb0a42b5a
1 changed files with 32 additions and 33 deletions
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@ -1178,7 +1178,7 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
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int reset_sof;
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int tag_sof;
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int t_wait = HITAG_T_WAIT_MAX;
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bool bStop;
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bool bStop = false;
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bool bQuitTraceFull = false;
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int sendNum = 0;
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unsigned char mask = 1;
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@ -1211,8 +1211,6 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
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} break;
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}
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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// Reset the return status
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bSuccessful = false;
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@ -1257,9 +1255,11 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
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// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
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// external trigger rising edge, load RA on falling edge of TIOA.
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AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
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| AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
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AT91C_BASE_TC1->TC_CMR =
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AT91C_TC_CLKS_TIMER_DIV1_CLOCK |
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AT91C_TC_ETRGEDG_FALLING |
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AT91C_TC_ABETRG |
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AT91C_TC_LDRA_FALLING;
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// Enable and reset counters
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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@ -1400,9 +1400,7 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
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// we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
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// All timer values are in terms of T0 units
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while (AT91C_BASE_TC0->TC_CV
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< T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit)))
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit))) {};
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// Transmit the reader frame
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hitag_reader_send_frame(tx, txlen);
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@ -1499,6 +1497,7 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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cmd_send(CMD_ACK, bSuccessful, 0, 0, 0, 0);
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}
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