chg: adjustments

This commit is contained in:
iceman1001 2018-02-28 08:04:53 +01:00
commit 8eb0a42b5a

View file

@ -1178,7 +1178,7 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
int reset_sof;
int tag_sof;
int t_wait = HITAG_T_WAIT_MAX;
bool bStop;
bool bStop = false;
bool bQuitTraceFull = false;
int sendNum = 0;
unsigned char mask = 1;
@ -1211,8 +1211,6 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
} break;
}
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
// Reset the return status
bSuccessful = false;
@ -1257,9 +1255,11 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
// external trigger rising edge, load RA on falling edge of TIOA.
AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
AT91C_BASE_TC1->TC_CMR =
AT91C_TC_CLKS_TIMER_DIV1_CLOCK |
AT91C_TC_ETRGEDG_FALLING |
AT91C_TC_ABETRG |
AT91C_TC_LDRA_FALLING;
// Enable and reset counters
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
@ -1400,9 +1400,7 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
// we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
// All timer values are in terms of T0 units
while (AT91C_BASE_TC0->TC_CV
< T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit)))
;
while (AT91C_BASE_TC0->TC_CV < T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit))) {};
// Transmit the reader frame
hitag_reader_send_frame(tx, txlen);
@ -1499,6 +1497,7 @@ void ReadHitagS(hitag_function htf, hitag_data* htd) {
AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
cmd_send(CMD_ACK, bSuccessful, 0, 0, 0, 0);
}