mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-20 21:33:47 -07:00
fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.
This commit is contained in:
iceman1001
parent
e6c046e17c
commit
8df14408b8
7 changed files with 191 additions and 203 deletions
172
fpga/fpga_hf.v
172
fpga/fpga_hf.v
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@ -23,23 +23,28 @@
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`define FPGA_CMD_TRACE_ENABLE 2
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// Major modes:
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`define FPGA_MAJOR_MODE_HF_READER_TX 0
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`define FPGA_MAJOR_MODE_HF_READER_RX_XCORR 1
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`define FPGA_MAJOR_MODE_HF_SIMULATOR 2
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`define FPGA_MAJOR_MODE_HF_ISO14443A 3
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`define FPGA_MAJOR_MODE_HF_SNOOP 4
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`define FPGA_MAJOR_MODE_HF_ISO18092 5
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`define FPGA_MAJOR_MODE_HF_GET_TRACE 6
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`define FPGA_MAJOR_MODE_HF_READER 0
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`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
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`define FPGA_MAJOR_MODE_HF_ISO14443A 2
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`define FPGA_MAJOR_MODE_HF_SNOOP 3
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`define FPGA_MAJOR_MODE_HF_ISO18092 4
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`define FPGA_MAJOR_MODE_HF_GET_TRACE 5
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`define FPGA_MAJOR_MODE_OFF 7
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// Options for the generic HF reader
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// Options for the HF reader, tx to tag
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`define FPGA_HF_READER_TX_SHALLOW_MOD 1
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`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
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`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
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`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
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`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
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`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
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`define FPGA_HF_READER_MODE_SNIFF_IQ 5
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`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
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`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
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`define FPGA_HF_READER_MODE_SEND_JAM 8
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// Options for the HF reader, correlating against rx from tag
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`define FPGA_HF_READER_RX_XCORR_848_KHZ 1
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`define FPGA_HF_READER_RX_XCORR_SNOOP 2
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`define FPGA_HF_READER_RX_XCORR_QUARTER 4
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`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
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`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
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`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
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// Options for the HF simulated tag, how to modulate
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`define FPGA_HF_SIMULATOR_NO_MODULATION 0
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@ -60,13 +65,12 @@
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`define FPGA_HF_ISO18092_FLAG_424K 2 // 0010 should enable 414k mode (untested). No autodetect
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`define FPGA_HF_ISO18092_FLAG_READER 4 // 0100 enables antenna power, to act as a reader instead of tag
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`include "hi_read_tx.v"
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`include "hi_read_rx_xcorr.v"
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`include "hi_reader.v"
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`include "hi_simulate.v"
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`include "hi_iso14443a.v"
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`include "hi_sniffer.v"
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`include "util.v"
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`include "hi_flite.v"
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// `include "hi_flite.v"
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`include "hi_get_trace.v"
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module fpga_hf(
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@ -105,14 +109,14 @@ bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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-----+-------------------------------------------
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cmd | x x x x
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major| x x x
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opt | x x
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opt | x x x
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divi | x x x x x x x x
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thres| x x x x x x x x
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-----+-------------------------------------------
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*/
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reg [15:0] shift_reg;
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reg [7:0] conf_word;
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reg [8:0] conf_word;
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reg trace_enable;
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// We switch modes between transmitting to the 13.56 MHz tag and receiving
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@ -121,7 +125,7 @@ reg trace_enable;
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always @(posedge ncs)
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begin
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case(shift_reg[15:12])
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`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[7:0];
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`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
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`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
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endcase
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end
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@ -135,25 +139,12 @@ begin
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end
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end
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wire [2:0] major_mode = conf_word[7:5];
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// select module (outputs) based on major mode
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wire [2:0] major_mode = conf_word[8:6];
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// For the high-frequency transmit configuration: modulation depth, either
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// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
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// some fraction of the buffers)
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wire hi_read_tx_shallow_modulation = conf_word[0];
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// For the high-frequency receive correlator: frequency against which to
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// correlate.
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wire hi_read_rx_xcorr_848 = conf_word[0];
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// and whether to drive the coil (reader) or just short it (snooper)
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wire hi_read_rx_xcorr_snoop = conf_word[1];
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// divide subcarrier frequency by 4
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wire hi_read_rx_xcorr_quarter = conf_word[2];
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// For the high-frequency simulated tag: what kind of modulation to use.
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wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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// configuring the HF reader
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wire [1:0] subcarrier_frequency = conf_word[5:4];
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wire [3:0] minor_mode = conf_word[3:0];
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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@ -161,95 +152,86 @@ wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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// the output pins.
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//-----------------------------------------------------------------------------
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hi_read_tx ht(
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pck0, ck_1356meg, ck_1356megb,
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ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
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adc_d, ht_adc_clk,
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ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
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cross_hi, cross_lo,
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ht_dbg,
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hi_read_tx_shallow_modulation
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);
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hi_read_rx_xcorr hrxc(
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pck0, ck_1356meg, ck_1356megb,
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hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
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adc_d, hrxc_adc_clk,
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hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
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cross_hi, cross_lo,
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hrxc_dbg,
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
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// 000 - HF reader
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hi_reader hr(
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ck_1356megb,
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hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
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adc_d, hr_adc_clk,
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hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
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hr_dbg,
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subcarrier_frequency, minor_mode
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);
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// 001 - HF simulated tag
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hi_simulate hs(
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pck0, ck_1356meg, ck_1356megb,
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ck_1356meg,
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hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
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adc_d, hs_adc_clk,
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hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
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cross_hi, cross_lo,
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hs_dbg,
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hi_simulate_mod_type
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minor_mode
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);
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// 010 - HF ISO14443-A
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hi_iso14443a hisn(
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pck0, ck_1356meg, ck_1356megb,
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ck_1356meg,
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hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
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adc_d, hisn_adc_clk,
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hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
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cross_hi, cross_lo,
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hisn_dbg,
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hi_simulate_mod_type
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minor_mode
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);
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// 011 - HF sniff
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hi_sniffer he(
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pck0, ck_1356meg, ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
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cross_hi, cross_lo,
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he_dbg,
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
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ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, he_ssp_clk
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);
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// 100 - HF ISO18092 FeliCa
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/*
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hi_flite hfl(
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pck0, ck_1356meg, ck_1356megb,
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hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
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adc_d, hfl_adc_clk,
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hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
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cross_hi, cross_lo,
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hfl_dbg,
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hi_simulate_mod_type
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ck_1356megb,
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hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
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adc_d, hfl_adc_clk,
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hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
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hfl_dbg,
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minor_mode
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);
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*/
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// 101 - HF get trace
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hi_get_trace gt(
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ck_1356megb,
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adc_d, trace_enable, major_mode,
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gt_ssp_frame, gt_ssp_din, gt_ssp_clk
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);
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// Major modes:
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// 000 -- HF reader; subcarrier frequency and modulation depth selectable
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// 001 -- HF simulated tag
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// 010 -- HF ISO14443-A
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// 011 -- HF sniff
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// 100 -- HF ISO18092 FeliCa
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// 101 -- HF get trace
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// 110 -- unused
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// 111 -- FPGA_MAJOR_MODE_OFF
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// 000 -- HF reader, transmitting to tag; modulation depth selectable
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// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
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// 010 -- HF simulated tag
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// 011 -- HF ISO14443-A
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// 100 -- HF Snoop
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// 101 -- Felica modem, reusing HF reader
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// 110 -- HF get trace
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// 111 -- everything off
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// 000 001 010 011 100 101 110 111
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mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, gt_ssp_din, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0);
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mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, gt_ssp_din, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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