mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-19 21:03:48 -07:00
new coverity scan complains..
fix 'lf hitag' bit comparisions wrong fix 'standalone mode' logically dead code
This commit is contained in:
iceman1001
parent
4406f4ee2a
commit
8bc17414fd
6 changed files with 150 additions and 146 deletions
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@ -574,8 +574,6 @@ void StandAloneMode14a()
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LED(selected + 1, 0);
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// Begin transmitting
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if (playing)
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{
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LED(LED_GREEN, 0);
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DbpString("Playing");
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for ( ; ; ) {
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@ -636,10 +634,7 @@ void StandAloneMode14a()
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SpinDelay(300);
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LEDsoff();
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LED(selected + 1, 0);
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}
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else
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while(BUTTON_PRESS())
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WDT_HIT();
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}
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}
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}
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129
armsrc/hitagS.c
129
armsrc/hitagS.c
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@ -167,25 +167,25 @@ static void hitag_send_bit(int bit) {
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if (bit == 0) {
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// AC Coding --__
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 32)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 32) {};
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 64)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 64) {};
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} else {
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// AC coding -_-_
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 16)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 16) {};
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 32)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 32) {};
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 48)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 48) {};
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 64)
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;;
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while (AT91C_BASE_TC0->TC_CV < T0 * 64) {};
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}
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LED_A_OFF();
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break;
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@ -193,25 +193,24 @@ static void hitag_send_bit(int bit) {
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if (bit == 0) {
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// AC Coding --__
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * HITAG_T_TAG_HALF_PERIOD)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * HITAG_T_TAG_HALF_PERIOD) {};
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * HITAG_T_TAG_FULL_PERIOD)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * HITAG_T_TAG_FULL_PERIOD) {};
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} else {
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// AC coding -_-_
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 8)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 8) {};
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 16)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 16) {};
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 24)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 24) {};
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 32)
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;;
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while (AT91C_BASE_TC0->TC_CV < T0 * 32) {};
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}
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LED_A_OFF();
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break;
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@ -219,19 +218,19 @@ static void hitag_send_bit(int bit) {
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if (bit == 0) {
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// Manchester: Unloaded, then loaded |__--|
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 16)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 16) {};
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 32)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 32) {};
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} else {
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// Manchester: Loaded, then unloaded |--__|
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 16)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 16) {};
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 32)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 32) {};
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}
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LED_A_OFF();
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break;
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@ -239,19 +238,19 @@ static void hitag_send_bit(int bit) {
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if (bit == 0) {
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// Manchester: Unloaded, then loaded |__--|
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 8)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 8) {};
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 16)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 16) {};
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} else {
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// Manchester: Loaded, then unloaded |--__|
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HIGH(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 8)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 8) {};
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LOW(GPIO_SSC_DOUT);
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while (AT91C_BASE_TC0->TC_CV < T0 * 16)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 16) {};
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}
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LED_A_OFF();
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break;
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@ -288,8 +287,8 @@ static void hitag_reader_send_bit(int bit) {
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HIGH(GPIO_SSC_DOUT);
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if (test == 1) {
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// Wait for 4-10 times the carrier period
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while (AT91C_BASE_TC0->TC_CV < T0 * 6)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 6) {};
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// SpinDelayUs(8*8);
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// Disable modulation, just activates the field again
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@ -297,19 +296,19 @@ static void hitag_reader_send_bit(int bit) {
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if (bit == 0) {
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// Zero bit: |_-|
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while (AT91C_BASE_TC0->TC_CV < T0 * 11)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 11) {};
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// SpinDelayUs(16*8);
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} else {
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// One bit: |_--|
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while (AT91C_BASE_TC0->TC_CV < T0 * 14)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 14) {};
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// SpinDelayUs(22*8);
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}
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} else {
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// Wait for 4-10 times the carrier period
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while (AT91C_BASE_TC0->TC_CV < T0 * 6)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 6) {};
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// SpinDelayUs(8*8);
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// Disable modulation, just activates the field again
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@ -317,13 +316,13 @@ static void hitag_reader_send_bit(int bit) {
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if (bit == 0) {
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// Zero bit: |_-|
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while (AT91C_BASE_TC0->TC_CV < T0 * 22)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 22) {};
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// SpinDelayUs(16*8);
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} else {
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// One bit: |_--|
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while (AT91C_BASE_TC0->TC_CV < T0 * 28)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 28) {};
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// SpinDelayUs(22*8);
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}
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}
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@ -344,8 +343,8 @@ static void hitag_reader_send_frame(const byte_t* frame, size_t frame_len) {
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// Enable modulation, which means, drop the the field
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HIGH(GPIO_SSC_DOUT);
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// Wait for 4-10 times the carrier period
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while (AT91C_BASE_TC0->TC_CV < T0 * 6)
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;
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while (AT91C_BASE_TC0->TC_CV < T0 * 6) {};
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// Disable modulation, just activates the field again
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LOW(GPIO_SSC_DOUT);
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}
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@ -988,39 +987,39 @@ void SimulateHitagSTag(bool tag_mem_supplied, byte_t* data) {
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tag.max_page=0;
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//con1
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tag.auth=0;
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if((tag.pages[1][2]&0x80)==1)
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if((tag.pages[1][2]&0x80) == 0x80)
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tag.auth=1;
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tag.LCON=0;
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if((tag.pages[1][2]&0x2)==1)
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if((tag.pages[1][2]&0x2) == 0x02)
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tag.LCON=1;
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tag.LKP=0;
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if((tag.pages[1][2]&0x1)==1)
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if((tag.pages[1][2]&0x1) == 0x01)
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tag.LKP=1;
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//con2
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//0=read write 1=read only
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tag.LCK7=0;
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if((tag.pages[1][1]&0x80)==1)
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if((tag.pages[1][1]&0x80) == 0x80)
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tag.LCK7=1;
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tag.LCK6=0;
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if((tag.pages[1][1]&0x40)==1)
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if((tag.pages[1][1]&0x40) == 0x040)
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tag.LCK6=1;
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tag.LCK5=0;
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if((tag.pages[1][1]&0x20)==1)
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if((tag.pages[1][1]&0x20) == 0x20)
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tag.LCK5=1;
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tag.LCK4=0;
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if((tag.pages[1][1]&0x10)==1)
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if((tag.pages[1][1]&0x10) == 0x10)
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tag.LCK4=1;
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tag.LCK3=0;
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if((tag.pages[1][1]&0x8)==1)
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if((tag.pages[1][1]&0x8) == 0x08)
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tag.LCK3=1;
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tag.LCK2=0;
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if((tag.pages[1][1]&0x4)==1)
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if((tag.pages[1][1]&0x4) == 0x04)
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tag.LCK2=1;
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tag.LCK1=0;
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if((tag.pages[1][1]&0x2)==1)
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if((tag.pages[1][1]&0x2) == 0x02)
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tag.LCK1=1;
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tag.LCK0=0;
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if((tag.pages[1][1]&0x1)==1)
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if((tag.pages[1][1]&0x1) == 0x01)
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tag.LCK0=1;
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// Set up simulator mode, frequency divisor which will drive the FPGA
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@ -879,11 +879,6 @@ int CmdHFSearch(const char *Cmd){
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PrintAndLog("\nValid ISO14443-A Tag Found - Quiting Search\n");
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return ans;
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}
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ans = HF14BReader(false); //CmdHF14BReader("s");
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if (ans) {
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PrintAndLog("\nValid ISO14443-B Tag Found - Quiting Search\n");
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return ans;
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}
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ans = HF15Reader("", false);
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if (ans) {
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PrintAndLog("\nValid ISO15693 Tag Found - Quiting Search\n");
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@ -899,6 +894,12 @@ int CmdHFSearch(const char *Cmd){
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PrintAndLog("\nValid Topaz Tag Found - Quiting Search\n");
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return 1;
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}
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// 14b and iclass is the longest test (put last)
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ans = HF14BReader(false); //CmdHF14BReader("s");
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if (ans) {
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PrintAndLog("\nValid ISO14443-B Tag Found - Quiting Search\n");
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return ans;
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}
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ans = HFiClassReader("", false, false);
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if (ans) {
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PrintAndLog("\nValid iClass Tag (or PicoPass Tag) Found - Quiting Search\n");
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@ -452,3 +452,6 @@ E241E8AFCBAF,
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# Data from forum post
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123F8888F322,
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050908080008,
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#
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# Data from hoist
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4f9f59c9c875,
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@ -15,9 +15,9 @@ module hi_read_rx_xcorr(
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk, ssp_frame, ssp_din;
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output adc_clk;
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input ssp_dout;
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output ssp_clk;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input xcorr_is_848, snoop;
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@ -28,11 +28,18 @@ assign pwr_oe1 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe4 = 1'b0;
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wire adc_clk = ck_1356megb;
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reg fc_div_2;
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// Clock divider
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reg [0:0] fc_divider;
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always @(negedge ck_1356megb)
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fc_div_2 <= fc_div_2 + 1;
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fc_divider <= fc_divider + 1;
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wire fc_div2 = fc_divider[0];
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reg adc_clk;
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always @(ck_1356megb)
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if (xcorr_is_848)
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adc_clk <= ck_1356megb;
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else
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adc_clk <= fc_div2;
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// When we're a reader, we just need to do the BPSK demod; but when we're an
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// eavesdropper, we also need to pick out the commands sent by the reader,
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@ -77,7 +84,6 @@ reg ssp_frame;
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always @(negedge adc_clk)
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begin
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if (xcorr_is_848 | fc_div_2)
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corr_i_cnt <= corr_i_cnt + 1;
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end
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@ -137,7 +143,7 @@ begin
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begin
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ssp_clk <= 1'b1;
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// Don't shift if we just loaded new data, obviously.
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if(corr_i_cnt != 7'd0)
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if(corr_i_cnt != 6'd0)
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begin
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corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
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corr_q_out[7:1] <= corr_q_out[6:0];
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