mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-21 05:43:48 -07:00
armsrc: fix mix of spaces & tabs
This commit is contained in:
Philippe Teuwen
parent
23f1a253a7
commit
8a7c6825b5
47 changed files with 18186 additions and 18184 deletions
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@ -21,7 +21,7 @@ extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
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static uint8_t *fpga_image_ptr = NULL;
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static uint32_t uncompressed_bytes_cnt;
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#define OUTPUT_BUFFER_LEN 80
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#define OUTPUT_BUFFER_LEN 80
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//-----------------------------------------------------------------------------
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// Set up the Serial Peripheral Interface as master
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@ -29,7 +29,7 @@ static uint32_t uncompressed_bytes_cnt;
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// May also be used to write to other SPI attached devices like an LCD
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//-----------------------------------------------------------------------------
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static void DisableSpi(void) {
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//* Reset all the Chip Select register
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//* Reset all the Chip Select register
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AT91C_BASE_SPI->SPI_CSR[0] = 0;
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AT91C_BASE_SPI->SPI_CSR[1] = 0;
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AT91C_BASE_SPI->SPI_CSR[2] = 0;
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@ -41,77 +41,77 @@ static void DisableSpi(void) {
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// Disable all interrupts
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AT91C_BASE_SPI->SPI_IDR = 0xFFFFFFFF;
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// SPI disable
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
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// SPI disable
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
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}
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void SetupSpi(int mode) {
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// PA1 -> SPI_NCS3 chip select (MEM)
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// PA10 -> SPI_NCS2 chip select (LCD)
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// PA11 -> SPI_NCS0 chip select (FPGA)
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// PA12 -> SPI_MISO Master-In Slave-Out
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// PA13 -> SPI_MOSI Master-Out Slave-In
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// PA14 -> SPI_SPCK Serial Clock
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// PA1 -> SPI_NCS3 chip select (MEM)
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// PA10 -> SPI_NCS2 chip select (LCD)
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// PA11 -> SPI_NCS0 chip select (FPGA)
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// PA12 -> SPI_MISO Master-In Slave-Out
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// PA13 -> SPI_MOSI Master-Out Slave-In
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// PA14 -> SPI_SPCK Serial Clock
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// Disable PIO control of the following pins, allows use by the SPI peripheral
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AT91C_BASE_PIOA->PIO_PDR = GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK;
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// Disable PIO control of the following pins, allows use by the SPI peripheral
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AT91C_BASE_PIOA->PIO_PDR = GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK;
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// Peripheral A
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AT91C_BASE_PIOA->PIO_ASR = GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK;
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// Peripheral A
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AT91C_BASE_PIOA->PIO_ASR = GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK;
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// Peripheral B
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//AT91C_BASE_PIOA->PIO_BSR |= GPIO_NCS2;
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// Peripheral B
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//AT91C_BASE_PIOA->PIO_BSR |= GPIO_NCS2;
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//enable the SPI Peripheral clock
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI);
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// Enable SPI
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
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//enable the SPI Peripheral clock
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI);
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// Enable SPI
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
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switch (mode) {
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case SPI_FPGA_MODE:
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AT91C_BASE_SPI->SPI_MR =
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(0xE << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
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( 0 << 7) | // Local Loopback Disabled
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AT91C_SPI_MODFDIS | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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AT91C_SPI_PS_FIXED | // Fixed Peripheral Select
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AT91C_SPI_MSTR; // Master Mode
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switch (mode) {
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case SPI_FPGA_MODE:
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AT91C_BASE_SPI->SPI_MR =
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(0xE << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
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( 0 << 7) | // Local Loopback Disabled
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AT91C_SPI_MODFDIS | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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AT91C_SPI_PS_FIXED | // Fixed Peripheral Select
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AT91C_SPI_MSTR; // Master Mode
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AT91C_BASE_SPI->SPI_CSR[0] =
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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AT91C_SPI_BITS_16 | // Bits per Transfer (16 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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AT91C_SPI_NCPHA | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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break;
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AT91C_BASE_SPI->SPI_CSR[0] =
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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AT91C_SPI_BITS_16 | // Bits per Transfer (16 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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AT91C_SPI_NCPHA | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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break;
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/*
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case SPI_LCD_MODE:
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AT91C_BASE_SPI->SPI_MR =
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(0xB << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
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( 0 << 7) | // Local Loopback Disabled
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( 1 << 4) | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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( 0 << 1) | // Fixed Peripheral Select
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( 1 << 0); // Master Mode
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case SPI_LCD_MODE:
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AT91C_BASE_SPI->SPI_MR =
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(0xB << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
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( 0 << 7) | // Local Loopback Disabled
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( 1 << 4) | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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( 0 << 1) | // Fixed Peripheral Select
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( 1 << 0); // Master Mode
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AT91C_BASE_SPI->SPI_CSR[2] =
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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AT91C_SPI_BITS_9 | // Bits per Transfer (9 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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break;
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AT91C_BASE_SPI->SPI_CSR[2] =
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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AT91C_SPI_BITS_9 | // Bits per Transfer (9 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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break;
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*/
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default:
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DisableSpi();
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break;
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}
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default:
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DisableSpi();
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break;
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}
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}
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//-----------------------------------------------------------------------------
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@ -119,35 +119,35 @@ void SetupSpi(int mode) {
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// always use when we are talking to the FPGA. Both RX and TX are enabled.
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//-----------------------------------------------------------------------------
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void FpgaSetupSsc(void) {
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// First configure the GPIOs, and get ourselves a clock.
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AT91C_BASE_PIOA->PIO_ASR =
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GPIO_SSC_FRAME |
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GPIO_SSC_DIN |
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GPIO_SSC_DOUT |
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GPIO_SSC_CLK;
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AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
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// First configure the GPIOs, and get ourselves a clock.
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AT91C_BASE_PIOA->PIO_ASR =
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GPIO_SSC_FRAME |
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GPIO_SSC_DIN |
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GPIO_SSC_DOUT |
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GPIO_SSC_CLK;
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AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
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// Now set up the SSC proper, starting from a known state.
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AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
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// Now set up the SSC proper, starting from a known state.
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AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
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// RX clock comes from TX clock, RX starts when TX starts, data changes
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// on RX clock rising edge, sampled on falling edge
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AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
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// RX clock comes from TX clock, RX starts when TX starts, data changes
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// on RX clock rising edge, sampled on falling edge
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AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
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// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
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// pulse, no output sync
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
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// pulse, no output sync
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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// clock comes from TK pin, no clock output, outputs change on falling
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// edge of TK, sample on rising edge of TK, start on positive-going edge of sync
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AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
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// clock comes from TK pin, no clock output, outputs change on falling
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// edge of TK, sample on rising edge of TK, start on positive-going edge of sync
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AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
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// tx framing is the same as the rx framing
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AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
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// tx framing is the same as the rx framing
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AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
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AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
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AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
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}
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//-----------------------------------------------------------------------------
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@ -157,15 +157,15 @@ void FpgaSetupSsc(void) {
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// is in apps.h, because it should be inlined, for speed.
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//-----------------------------------------------------------------------------
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bool FpgaSetupSscDma(uint8_t *buf, int len) {
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if (buf == NULL) return false;
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if (buf == NULL) return false;
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FpgaDisableSscDma();
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AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
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AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
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AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
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AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
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FpgaEnableSscDma();
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return true;
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FpgaDisableSscDma();
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AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
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AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
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AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
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AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
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FpgaEnableSscDma();
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return true;
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}
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//----------------------------------------------------------------------------
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@ -173,20 +173,20 @@ bool FpgaSetupSscDma(uint8_t *buf, int len) {
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// each call.
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//----------------------------------------------------------------------------
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static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer) {
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if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
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compressed_fpga_stream->next_out = output_buffer;
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compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
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fpga_image_ptr = output_buffer;
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int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
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if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
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compressed_fpga_stream->next_out = output_buffer;
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compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
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fpga_image_ptr = output_buffer;
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int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
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if (res != Z_OK)
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Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
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if (res != Z_OK)
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Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
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if (res < 0)
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return res;
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}
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uncompressed_bytes_cnt++;
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return *fpga_image_ptr++;
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if (res < 0)
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return res;
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}
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uncompressed_bytes_cnt++;
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return *fpga_image_ptr++;
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}
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//----------------------------------------------------------------------------
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@ -195,140 +195,140 @@ static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8
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// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
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//----------------------------------------------------------------------------
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static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer) {
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while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % fpga_bitstream_num != (bitstream_version - 1)) {
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// skip undesired data belonging to other bitstream_versions
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get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
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}
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while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % fpga_bitstream_num != (bitstream_version - 1)) {
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// skip undesired data belonging to other bitstream_versions
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get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
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}
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return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
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return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
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}
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static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size) {
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return BigBuf_malloc(items*size);
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return BigBuf_malloc(items*size);
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}
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// free eventually allocated BigBuf memory
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static void fpga_inflate_free(voidpf opaque, voidpf address) {
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BigBuf_free(); BigBuf_Clear_ext(false);
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BigBuf_free(); BigBuf_Clear_ext(false);
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}
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//----------------------------------------------------------------------------
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// Initialize decompression of the respective (HF or LF) FPGA stream
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//----------------------------------------------------------------------------
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static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer) {
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uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
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uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
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uncompressed_bytes_cnt = 0;
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uncompressed_bytes_cnt = 0;
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// initialize z_stream structure for inflate:
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compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
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compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_end - &_binary_obj_fpga_all_bit_z_start;
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compressed_fpga_stream->next_out = output_buffer;
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compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
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compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
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compressed_fpga_stream->zfree = &fpga_inflate_free;
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// initialize z_stream structure for inflate:
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compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
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compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_end - &_binary_obj_fpga_all_bit_z_start;
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compressed_fpga_stream->next_out = output_buffer;
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compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
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compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
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compressed_fpga_stream->zfree = &fpga_inflate_free;
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inflateInit2(compressed_fpga_stream, 0);
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inflateInit2(compressed_fpga_stream, 0);
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fpga_image_ptr = output_buffer;
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fpga_image_ptr = output_buffer;
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for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++)
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header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
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for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++)
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header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
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// Check for a valid .bit file (starts with bitparse_fixed_header)
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if (memcmp(bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0)
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return true;
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// Check for a valid .bit file (starts with bitparse_fixed_header)
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if (memcmp(bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0)
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return true;
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return false;
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return false;
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}
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static void DownloadFPGA_byte( uint8_t w) {
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#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
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SEND_BIT(7);
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SEND_BIT(6);
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SEND_BIT(5);
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SEND_BIT(4);
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||||
SEND_BIT(3);
|
||||
SEND_BIT(2);
|
||||
SEND_BIT(1);
|
||||
SEND_BIT(0);
|
||||
SEND_BIT(7);
|
||||
SEND_BIT(6);
|
||||
SEND_BIT(5);
|
||||
SEND_BIT(4);
|
||||
SEND_BIT(3);
|
||||
SEND_BIT(2);
|
||||
SEND_BIT(1);
|
||||
SEND_BIT(0);
|
||||
}
|
||||
|
||||
// Download the fpga image starting at current stream position with length FpgaImageLen bytes
|
||||
static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer) {
|
||||
int i = 0;
|
||||
int i = 0;
|
||||
|
||||
AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
|
||||
AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
|
||||
HIGH(GPIO_FPGA_ON); // ensure everything is powered on
|
||||
AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
|
||||
AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
|
||||
HIGH(GPIO_FPGA_ON); // ensure everything is powered on
|
||||
|
||||
SpinDelay(50);
|
||||
SpinDelay(50);
|
||||
|
||||
LED_D_ON();
|
||||
LED_D_ON();
|
||||
|
||||
// These pins are inputs
|
||||
// These pins are inputs
|
||||
AT91C_BASE_PIOA->PIO_ODR =
|
||||
GPIO_FPGA_NINIT |
|
||||
GPIO_FPGA_DONE;
|
||||
// PIO controls the following pins
|
||||
GPIO_FPGA_NINIT |
|
||||
GPIO_FPGA_DONE;
|
||||
// PIO controls the following pins
|
||||
AT91C_BASE_PIOA->PIO_PER =
|
||||
GPIO_FPGA_NINIT |
|
||||
GPIO_FPGA_DONE;
|
||||
// Enable pull-ups
|
||||
AT91C_BASE_PIOA->PIO_PPUER =
|
||||
GPIO_FPGA_NINIT |
|
||||
GPIO_FPGA_DONE;
|
||||
GPIO_FPGA_NINIT |
|
||||
GPIO_FPGA_DONE;
|
||||
// Enable pull-ups
|
||||
AT91C_BASE_PIOA->PIO_PPUER =
|
||||
GPIO_FPGA_NINIT |
|
||||
GPIO_FPGA_DONE;
|
||||
|
||||
// setup initial logic state
|
||||
HIGH(GPIO_FPGA_NPROGRAM);
|
||||
LOW(GPIO_FPGA_CCLK);
|
||||
LOW(GPIO_FPGA_DIN);
|
||||
// These pins are outputs
|
||||
AT91C_BASE_PIOA->PIO_OER =
|
||||
GPIO_FPGA_NPROGRAM |
|
||||
GPIO_FPGA_CCLK |
|
||||
GPIO_FPGA_DIN;
|
||||
// setup initial logic state
|
||||
HIGH(GPIO_FPGA_NPROGRAM);
|
||||
LOW(GPIO_FPGA_CCLK);
|
||||
LOW(GPIO_FPGA_DIN);
|
||||
// These pins are outputs
|
||||
AT91C_BASE_PIOA->PIO_OER =
|
||||
GPIO_FPGA_NPROGRAM |
|
||||
GPIO_FPGA_CCLK |
|
||||
GPIO_FPGA_DIN;
|
||||
|
||||
// enter FPGA configuration mode
|
||||
LOW(GPIO_FPGA_NPROGRAM);
|
||||
SpinDelay(50);
|
||||
HIGH(GPIO_FPGA_NPROGRAM);
|
||||
// enter FPGA configuration mode
|
||||
LOW(GPIO_FPGA_NPROGRAM);
|
||||
SpinDelay(50);
|
||||
HIGH(GPIO_FPGA_NPROGRAM);
|
||||
|
||||
i = 100000;
|
||||
// wait for FPGA ready to accept data signal
|
||||
while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
|
||||
i--;
|
||||
}
|
||||
i = 100000;
|
||||
// wait for FPGA ready to accept data signal
|
||||
while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
|
||||
i--;
|
||||
}
|
||||
|
||||
// crude error indicator, leave both red LEDs on and return
|
||||
if (i==0){
|
||||
LED_C_ON();
|
||||
LED_D_ON();
|
||||
return;
|
||||
}
|
||||
// crude error indicator, leave both red LEDs on and return
|
||||
if (i==0){
|
||||
LED_C_ON();
|
||||
LED_D_ON();
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < FpgaImageLen; i++) {
|
||||
int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
||||
if (b < 0) {
|
||||
Dbprintf("Error %d during FpgaDownload", b);
|
||||
break;
|
||||
}
|
||||
DownloadFPGA_byte(b);
|
||||
}
|
||||
for (i = 0; i < FpgaImageLen; i++) {
|
||||
int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
||||
if (b < 0) {
|
||||
Dbprintf("Error %d during FpgaDownload", b);
|
||||
break;
|
||||
}
|
||||
DownloadFPGA_byte(b);
|
||||
}
|
||||
|
||||
// continue to clock FPGA until ready signal goes high
|
||||
i = 100000;
|
||||
while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
|
||||
HIGH(GPIO_FPGA_CCLK);
|
||||
LOW(GPIO_FPGA_CCLK);
|
||||
}
|
||||
// crude error indicator, leave both red LEDs on and return
|
||||
if (i==0){
|
||||
LED_C_ON();
|
||||
LED_D_ON();
|
||||
return;
|
||||
}
|
||||
LED_D_OFF();
|
||||
// continue to clock FPGA until ready signal goes high
|
||||
i = 100000;
|
||||
while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
|
||||
HIGH(GPIO_FPGA_CCLK);
|
||||
LOW(GPIO_FPGA_CCLK);
|
||||
}
|
||||
// crude error indicator, leave both red LEDs on and return
|
||||
if (i==0){
|
||||
LED_C_ON();
|
||||
LED_D_ON();
|
||||
return;
|
||||
}
|
||||
LED_D_OFF();
|
||||
}
|
||||
|
||||
/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
|
||||
|
|
@ -338,48 +338,48 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp comp
|
|||
* length.
|
||||
*/
|
||||
static int bitparse_find_section(int bitstream_version, char section_name, uint32_t *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer) {
|
||||
int result = 0;
|
||||
#define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
|
||||
uint16_t numbytes = 0;
|
||||
while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
|
||||
char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
||||
numbytes++;
|
||||
uint32_t current_length = 0;
|
||||
if (current_name < 'a' || current_name > 'e') {
|
||||
/* Strange section name, abort */
|
||||
break;
|
||||
}
|
||||
current_length = 0;
|
||||
switch (current_name) {
|
||||
case 'e':
|
||||
/* Four byte length field */
|
||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
|
||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
|
||||
numbytes += 2;
|
||||
default: /* Fall through, two byte length field */
|
||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
|
||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
|
||||
numbytes += 2;
|
||||
}
|
||||
int result = 0;
|
||||
#define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
|
||||
uint16_t numbytes = 0;
|
||||
while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
|
||||
char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
||||
numbytes++;
|
||||
uint32_t current_length = 0;
|
||||
if (current_name < 'a' || current_name > 'e') {
|
||||
/* Strange section name, abort */
|
||||
break;
|
||||
}
|
||||
current_length = 0;
|
||||
switch (current_name) {
|
||||
case 'e':
|
||||
/* Four byte length field */
|
||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
|
||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
|
||||
numbytes += 2;
|
||||
default: /* Fall through, two byte length field */
|
||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
|
||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
|
||||
numbytes += 2;
|
||||
}
|
||||
|
||||
if (current_name != 'e' && current_length > 255) {
|
||||
/* Maybe a parse error */
|
||||
break;
|
||||
}
|
||||
if (current_name != 'e' && current_length > 255) {
|
||||
/* Maybe a parse error */
|
||||
break;
|
||||
}
|
||||
|
||||
if (current_name == section_name) {
|
||||
/* Found it */
|
||||
*section_length = current_length;
|
||||
result = 1;
|
||||
break;
|
||||
}
|
||||
if (current_name == section_name) {
|
||||
/* Found it */
|
||||
*section_length = current_length;
|
||||
result = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
|
||||
get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
||||
numbytes++;
|
||||
}
|
||||
}
|
||||
return result;
|
||||
for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
|
||||
get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
||||
numbytes++;
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
|
@ -388,34 +388,34 @@ static int bitparse_find_section(int bitstream_version, char section_name, uint3
|
|||
//----------------------------------------------------------------------------
|
||||
void FpgaDownloadAndGo(int bitstream_version) {
|
||||
|
||||
// check whether or not the bitstream is already loaded
|
||||
if (downloaded_bitstream == bitstream_version)
|
||||
return;
|
||||
// check whether or not the bitstream is already loaded
|
||||
if (downloaded_bitstream == bitstream_version)
|
||||
return;
|
||||
|
||||
z_stream compressed_fpga_stream;
|
||||
uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
|
||||
z_stream compressed_fpga_stream;
|
||||
uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
|
||||
|
||||
bool verbose = (MF_DBGLEVEL > 3);
|
||||
bool verbose = (MF_DBGLEVEL > 3);
|
||||
|
||||
// make sure that we have enough memory to decompress
|
||||
BigBuf_free(); BigBuf_Clear_ext(verbose);
|
||||
// make sure that we have enough memory to decompress
|
||||
BigBuf_free(); BigBuf_Clear_ext(verbose);
|
||||
|
||||
if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer))
|
||||
return;
|
||||
if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer))
|
||||
return;
|
||||
|
||||
uint32_t bitstream_length;
|
||||
if (bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
|
||||
DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
|
||||
downloaded_bitstream = bitstream_version;
|
||||
}
|
||||
uint32_t bitstream_length;
|
||||
if (bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
|
||||
DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
|
||||
downloaded_bitstream = bitstream_version;
|
||||
}
|
||||
|
||||
inflateEnd(&compressed_fpga_stream);
|
||||
inflateEnd(&compressed_fpga_stream);
|
||||
|
||||
// turn off antenna
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
// turn off antenna
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
|
||||
// free eventually allocated BigBuf memory
|
||||
BigBuf_free(); BigBuf_Clear_ext(false);
|
||||
// free eventually allocated BigBuf memory
|
||||
BigBuf_free(); BigBuf_Clear_ext(false);
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
|
|
@ -424,10 +424,10 @@ void FpgaDownloadAndGo(int bitstream_version) {
|
|||
// where C is the 4 bit command and D is the 12 bit data
|
||||
//-----------------------------------------------------------------------------
|
||||
void FpgaSendCommand(uint16_t cmd, uint16_t v) {
|
||||
SetupSpi(SPI_FPGA_MODE);
|
||||
while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
|
||||
AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
|
||||
while (!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RDRF)) {}; // wait till transfer is complete
|
||||
SetupSpi(SPI_FPGA_MODE);
|
||||
while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
|
||||
AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
|
||||
while (!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RDRF)) {}; // wait till transfer is complete
|
||||
}
|
||||
//-----------------------------------------------------------------------------
|
||||
// Write the FPGA setup word (that determines what mode the logic is in, read
|
||||
|
|
@ -435,7 +435,7 @@ void FpgaSendCommand(uint16_t cmd, uint16_t v) {
|
|||
// avoid changing this function's occurence everywhere in the source code.
|
||||
//-----------------------------------------------------------------------------
|
||||
void FpgaWriteConfWord(uint8_t v) {
|
||||
FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
|
||||
FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
|
|
@ -444,35 +444,35 @@ void FpgaWriteConfWord(uint8_t v) {
|
|||
// the samples from the ADC always flow through the FPGA.
|
||||
//-----------------------------------------------------------------------------
|
||||
void SetAdcMuxFor(uint32_t whichGpio) {
|
||||
AT91C_BASE_PIOA->PIO_OER =
|
||||
GPIO_MUXSEL_HIPKD |
|
||||
GPIO_MUXSEL_LOPKD |
|
||||
GPIO_MUXSEL_LORAW |
|
||||
GPIO_MUXSEL_HIRAW;
|
||||
AT91C_BASE_PIOA->PIO_OER =
|
||||
GPIO_MUXSEL_HIPKD |
|
||||
GPIO_MUXSEL_LOPKD |
|
||||
GPIO_MUXSEL_LORAW |
|
||||
GPIO_MUXSEL_HIRAW;
|
||||
|
||||
AT91C_BASE_PIOA->PIO_PER =
|
||||
GPIO_MUXSEL_HIPKD |
|
||||
GPIO_MUXSEL_LOPKD |
|
||||
GPIO_MUXSEL_LORAW |
|
||||
GPIO_MUXSEL_HIRAW;
|
||||
AT91C_BASE_PIOA->PIO_PER =
|
||||
GPIO_MUXSEL_HIPKD |
|
||||
GPIO_MUXSEL_LOPKD |
|
||||
GPIO_MUXSEL_LORAW |
|
||||
GPIO_MUXSEL_HIRAW;
|
||||
|
||||
LOW(GPIO_MUXSEL_HIPKD);
|
||||
LOW(GPIO_MUXSEL_LOPKD);
|
||||
LOW(GPIO_MUXSEL_HIPKD);
|
||||
LOW(GPIO_MUXSEL_LOPKD);
|
||||
#ifndef WITH_FPC
|
||||
LOW(GPIO_MUXSEL_HIRAW);
|
||||
LOW(GPIO_MUXSEL_LORAW);
|
||||
LOW(GPIO_MUXSEL_HIRAW);
|
||||
LOW(GPIO_MUXSEL_LORAW);
|
||||
#endif
|
||||
|
||||
HIGH(whichGpio);
|
||||
HIGH(whichGpio);
|
||||
}
|
||||
|
||||
void Fpga_print_status(void) {
|
||||
Dbprintf("Currently loaded FPGA image");
|
||||
Dbprintf(" mode....................%s", fpga_version_information[downloaded_bitstream-1]);
|
||||
Dbprintf("Currently loaded FPGA image");
|
||||
Dbprintf(" mode....................%s", fpga_version_information[downloaded_bitstream-1]);
|
||||
}
|
||||
|
||||
int FpgaGetCurrent(void) {
|
||||
return downloaded_bitstream;
|
||||
return downloaded_bitstream;
|
||||
}
|
||||
|
||||
// Turns off the antenna,
|
||||
|
|
@ -480,10 +480,10 @@ int FpgaGetCurrent(void) {
|
|||
// if HF, Disable SSC DMA
|
||||
// turn off trace and leds off.
|
||||
void switch_off(void) {
|
||||
if (MF_DBGLEVEL > 3) Dbprintf("switch_off");
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
if (downloaded_bitstream == FPGA_BITSTREAM_HF )
|
||||
FpgaDisableSscDma();
|
||||
set_tracing(false);
|
||||
LEDsoff();
|
||||
if (MF_DBGLEVEL > 3) Dbprintf("switch_off");
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
if (downloaded_bitstream == FPGA_BITSTREAM_HF )
|
||||
FpgaDisableSscDma();
|
||||
set_tracing(false);
|
||||
LEDsoff();
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue