mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-14 18:48:13 -07:00
armsrc: fix mix of spaces & tabs
This commit is contained in:
parent
23f1a253a7
commit
8a7c6825b5
47 changed files with 18186 additions and 18184 deletions
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@ -18,118 +18,118 @@ void FlashmemSetSpiBaudrate(uint32_t baudrate){
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Dbprintf("Spi Baudrate : %dMhz", FLASHMEM_SPIBAUDRATE/1000000);
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}
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// initialize
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// initialize
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bool FlashInit() {
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FlashSetup(FLASHMEM_SPIBAUDRATE);
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FlashSetup(FLASHMEM_SPIBAUDRATE);
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StartTicks();
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StartTicks();
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if (Flash_CheckBusy(BUSY_TIMEOUT)) {
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StopTicks();
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return false;
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}
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if (Flash_CheckBusy(BUSY_TIMEOUT)) {
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StopTicks();
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return false;
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}
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return true;
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return true;
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}
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void FlashSetup(uint32_t baudrate){
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//WDT_DISABLE
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AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
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// PA10 -> SPI_NCS2 chip select (FLASHMEM)
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// PA11 -> SPI_NCS0 chip select (FPGA)
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// PA12 -> SPI_MISO Master-In Slave-Out
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// PA13 -> SPI_MOSI Master-Out Slave-In
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// PA14 -> SPI_SPCK Serial Clock
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// PA10 -> SPI_NCS2 chip select (FLASHMEM)
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// PA11 -> SPI_NCS0 chip select (FPGA)
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// PA12 -> SPI_MISO Master-In Slave-Out
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// PA13 -> SPI_MOSI Master-Out Slave-In
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// PA14 -> SPI_SPCK Serial Clock
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// Disable PIO control of the following pins, allows use by the SPI peripheral
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AT91C_BASE_PIOA->PIO_PDR |= (GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK | GPIO_NCS2);
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// Disable PIO control of the following pins, allows use by the SPI peripheral
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AT91C_BASE_PIOA->PIO_PDR |= (GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK | GPIO_NCS2);
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// Pull-up Enable
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AT91C_BASE_PIOA->PIO_PPUER |= (GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK | GPIO_NCS2);
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// Pull-up Enable
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AT91C_BASE_PIOA->PIO_PPUER |= (GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK | GPIO_NCS2);
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// Peripheral A
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AT91C_BASE_PIOA->PIO_ASR |= (GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK);
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// Peripheral A
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AT91C_BASE_PIOA->PIO_ASR |= (GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK);
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// Peripheral B
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AT91C_BASE_PIOA->PIO_BSR |= GPIO_NCS2;
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// Peripheral B
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AT91C_BASE_PIOA->PIO_BSR |= GPIO_NCS2;
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//enable the SPI Peripheral clock
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI);
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//enable the SPI Peripheral clock
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI);
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//reset spi needs double SWRST, see atmel's errata on this case
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
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//reset spi needs double SWRST, see atmel's errata on this case
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
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// Enable SPI
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
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// Enable SPI
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
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// NPCS2 Mode 0
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AT91C_BASE_SPI->SPI_MR =
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(0 << 24) | // Delay between chip selects = DYLBCS/MCK BUT:
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// If DLYBCS is less than or equal to six, six MCK periods
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// will be inserted by default.
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SPI_PCS(SPI_CSR_NUM) | // Peripheral Chip Select (selects SPI_NCS2 or PA10)
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( 0 << 7) | // Disable LLB (1=MOSI2MISO test mode)
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( 1 << 4) | // Disable ModeFault Protection
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( 0 << 3) | // makes spi operate at MCK (1 is MCK/2)
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( 0 << 2) | // Chip selects connected directly to peripheral
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AT91C_SPI_PS_FIXED | // Fixed Peripheral Select
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AT91C_SPI_MSTR; // Master Mode
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// NPCS2 Mode 0
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AT91C_BASE_SPI->SPI_MR =
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(0 << 24) | // Delay between chip selects = DYLBCS/MCK BUT:
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// If DLYBCS is less than or equal to six, six MCK periods
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// will be inserted by default.
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SPI_PCS(SPI_CSR_NUM) | // Peripheral Chip Select (selects SPI_NCS2 or PA10)
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( 0 << 7) | // Disable LLB (1=MOSI2MISO test mode)
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( 1 << 4) | // Disable ModeFault Protection
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( 0 << 3) | // makes spi operate at MCK (1 is MCK/2)
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( 0 << 2) | // Chip selects connected directly to peripheral
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AT91C_SPI_PS_FIXED | // Fixed Peripheral Select
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AT91C_SPI_MSTR; // Master Mode
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uint8_t csaat = 1;
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uint32_t dlybct = 0;
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uint8_t csaat = 1;
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uint32_t dlybct = 0;
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if (baudrate > FLASH_MINFAST) {
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baudrate = FLASH_FASTBAUD;
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//csaat = 0;
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dlybct = 1500;
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}
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baudrate = FLASH_FASTBAUD;
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//csaat = 0;
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dlybct = 1500;
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}
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AT91C_BASE_SPI->SPI_CSR[2] =
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SPI_DLYBCT(dlybct,MCK) | // Delay between Consecutive Transfers (32 MCK periods)
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SPI_DLYBS(0,MCK) | // Delay Beforce SPCK CLock
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SPI_SCBR(baudrate,MCK) | // SPI Baudrate Selection
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AT91C_SPI_BITS_8 | // Bits per Transfer (8 bits)
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//AT91C_SPI_CSAAT | // Chip Select inactive after transfer
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// 40.4.6.2 SPI: Bad tx_ready Behavior when CSAAT = 1 and SCBR = 1
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// If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on
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// the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been
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// transferred in the shifter. This can imply for example, that the second data is sent twice.
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// COLIN :: For now we STILL use CSAAT=1 to avoid having to (de)assert NPCS manually via PIO lines and we deal with delay
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( csaat << 3) |
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/* Spi modes:
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Mode CPOL CPHA NCPHA
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0 0 0 1 clock normally low read on rising edge
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1 0 1 0 clock normally low read on falling edge
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2 1 0 1 clock normally high read on falling edge
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3 1 1 0 clock normally high read on rising edge
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However, page 512 of the AT91SAM7Sx datasheet say "Note that in SPI
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master mode the ATSAM7S512/256/128/64/321/32 does not sample the data
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(MISO) on the opposite edge where data clocks out (MOSI) but the same
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edge is used as shown in Figure 36-3 and Figure 36-4." Figure 36-3
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shows that CPOL=NCPHA=0 or CPOL=NCPHA=1 samples on the rising edge and
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that the data changes sometime after the rising edge (about 2 ns). To
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be consistent with normal SPI operation, it is probably safe to say
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that the data changes on the falling edge and should be sampled on the
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rising edge. Therefore, it appears that NCPHA should be treated the
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same as CPHA. Thus:
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Mode CPOL CPHA NCPHA
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0 0 0 0 clock normally low read on rising edge
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1 0 1 1 clock normally low read on falling edge
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2 1 0 0 clock normally high read on falling edge
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3 1 1 1 clock normally high read on rising edge
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*/
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( 0 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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AT91C_BASE_SPI->SPI_CSR[2] =
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SPI_DLYBCT(dlybct,MCK)| // Delay between Consecutive Transfers (32 MCK periods)
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SPI_DLYBS(0,MCK) | // Delay Beforce SPCK CLock
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SPI_SCBR(baudrate,MCK)| // SPI Baudrate Selection
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AT91C_SPI_BITS_8 | // Bits per Transfer (8 bits)
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//AT91C_SPI_CSAAT | // Chip Select inactive after transfer
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// 40.4.6.2 SPI: Bad tx_ready Behavior when CSAAT = 1 and SCBR = 1
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// If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on
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// the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been
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// transferred in the shifter. This can imply for example, that the second data is sent twice.
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// COLIN :: For now we STILL use CSAAT=1 to avoid having to (de)assert NPCS manually via PIO lines and we deal with delay
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( csaat << 3) |
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/* Spi modes:
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Mode CPOL CPHA NCPHA
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0 0 0 1 clock normally low read on rising edge
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1 0 1 0 clock normally low read on falling edge
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2 1 0 1 clock normally high read on falling edge
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3 1 1 0 clock normally high read on rising edge
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However, page 512 of the AT91SAM7Sx datasheet say "Note that in SPI
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master mode the ATSAM7S512/256/128/64/321/32 does not sample the data
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(MISO) on the opposite edge where data clocks out (MOSI) but the same
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edge is used as shown in Figure 36-3 and Figure 36-4." Figure 36-3
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shows that CPOL=NCPHA=0 or CPOL=NCPHA=1 samples on the rising edge and
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that the data changes sometime after the rising edge (about 2 ns). To
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be consistent with normal SPI operation, it is probably safe to say
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that the data changes on the falling edge and should be sampled on the
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rising edge. Therefore, it appears that NCPHA should be treated the
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same as CPHA. Thus:
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Mode CPOL CPHA NCPHA
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0 0 0 0 clock normally low read on rising edge
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1 0 1 1 clock normally low read on falling edge
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2 1 0 0 clock normally high read on falling edge
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3 1 1 1 clock normally high read on rising edge
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*/
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( 0 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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// read first, empty buffer
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if (AT91C_BASE_SPI->SPI_RDR == 0) {};
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// read first, empty buffer
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if (AT91C_BASE_SPI->SPI_RDR == 0) {};
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}
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void FlashStop(void) {
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//Bof
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//* Reset all the Chip Select register
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//Bof
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//* Reset all the Chip Select register
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AT91C_BASE_SPI->SPI_CSR[0] = 0;
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AT91C_BASE_SPI->SPI_CSR[1] = 0;
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AT91C_BASE_SPI->SPI_CSR[2] = 0;
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@ -141,164 +141,164 @@ void FlashStop(void) {
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// Disable all interrupts
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AT91C_BASE_SPI->SPI_IDR = 0xFFFFFFFF;
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// SPI disable
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
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// SPI disable
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
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if ( MF_DBGLEVEL > 3 ) Dbprintf("FlashStop");
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if ( MF_DBGLEVEL > 3 ) Dbprintf("FlashStop");
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StopTicks();
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StopTicks();
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}
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// send one byte over SPI
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// send one byte over SPI
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uint16_t FlashSendByte(uint32_t data) {
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// wait until SPI is ready for transfer
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//if you are checking for incoming data returned then the TXEMPTY flag is redundant
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//while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0) {};
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// wait until SPI is ready for transfer
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//if you are checking for incoming data returned then the TXEMPTY flag is redundant
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//while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0) {};
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// send the data
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AT91C_BASE_SPI->SPI_TDR = data;
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// send the data
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AT91C_BASE_SPI->SPI_TDR = data;
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//while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TDRE) == 0){};
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// wait recive transfer is complete
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while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RDRF) == 0){};
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// wait recive transfer is complete
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while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RDRF) == 0){};
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// reading incoming data
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return ((AT91C_BASE_SPI->SPI_RDR) & 0xFFFF);
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// reading incoming data
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return ((AT91C_BASE_SPI->SPI_RDR) & 0xFFFF);
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}
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// send last byte over SPI
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// send last byte over SPI
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uint16_t FlashSendLastByte(uint32_t data) {
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return FlashSendByte(data | AT91C_SPI_LASTXFER);
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return FlashSendByte(data | AT91C_SPI_LASTXFER);
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}
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// read state register 1
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// read state register 1
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uint8_t Flash_ReadStat1(void) {
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FlashSendByte(READSTAT1);
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return FlashSendLastByte(0xFF);
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FlashSendByte(READSTAT1);
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return FlashSendLastByte(0xFF);
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}
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bool Flash_CheckBusy(uint32_t timeout)
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{
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WaitUS(WINBOND_WRITE_DELAY);
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StartCountUS();
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uint32_t _time = GetCountUS();
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WaitUS(WINBOND_WRITE_DELAY);
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StartCountUS();
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uint32_t _time = GetCountUS();
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if ( MF_DBGLEVEL > 3 ) Dbprintf("Checkbusy in...");
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if ( MF_DBGLEVEL > 3 ) Dbprintf("Checkbusy in...");
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do
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{
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if (!(Flash_ReadStat1() & BUSY))
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{
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return false;
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}
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} while ((GetCountUS() - _time) < timeout);
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do
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{
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if (!(Flash_ReadStat1() & BUSY))
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{
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return false;
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}
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} while ((GetCountUS() - _time) < timeout);
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if (timeout <= (GetCountUS() - _time))
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{
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return true;
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}
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if (timeout <= (GetCountUS() - _time))
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{
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return true;
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}
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return false;
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return false;
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}
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// read ID out
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uint8_t Flash_ReadID(void) {
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if (Flash_CheckBusy(BUSY_TIMEOUT)) return 0;
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if (Flash_CheckBusy(BUSY_TIMEOUT)) return 0;
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// Manufacture ID / device ID
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FlashSendByte(ID);
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FlashSendByte(0x00);
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FlashSendByte(0x00);
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FlashSendByte(0x00);
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// Manufacture ID / device ID
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FlashSendByte(ID);
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FlashSendByte(0x00);
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FlashSendByte(0x00);
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FlashSendByte(0x00);
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uint8_t man_id = FlashSendByte(0xFF);
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uint8_t dev_id = FlashSendLastByte(0xFF);
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uint8_t dev_id = FlashSendLastByte(0xFF);
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if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash ReadID | Man ID %02x | Device ID %02x", man_id, dev_id);
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if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash ReadID | Man ID %02x | Device ID %02x", man_id, dev_id);
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if ( (man_id == WINBOND_MANID ) && (dev_id == WINBOND_DEVID) )
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return dev_id;
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if ( (man_id == WINBOND_MANID ) && (dev_id == WINBOND_DEVID) )
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return dev_id;
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return 0;
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return 0;
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}
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// read unique id for chip.
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void Flash_UniqueID(uint8_t *uid) {
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if (Flash_CheckBusy(BUSY_TIMEOUT)) return;
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if (Flash_CheckBusy(BUSY_TIMEOUT)) return;
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// reading unique serial number
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FlashSendByte(UNIQUE_ID);
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FlashSendByte(0xFF);
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FlashSendByte(0xFF);
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FlashSendByte(0xFF);
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FlashSendByte(0xFF);
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// reading unique serial number
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FlashSendByte(UNIQUE_ID);
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FlashSendByte(0xFF);
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FlashSendByte(0xFF);
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FlashSendByte(0xFF);
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FlashSendByte(0xFF);
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uid[7] = FlashSendByte(0xFF);
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uid[6] = FlashSendByte(0xFF);
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uid[5] = FlashSendByte(0xFF);
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uid[4] = FlashSendByte(0xFF);
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uid[7] = FlashSendByte(0xFF);
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uid[6] = FlashSendByte(0xFF);
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uid[5] = FlashSendByte(0xFF);
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uid[4] = FlashSendByte(0xFF);
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uid[3] = FlashSendByte(0xFF);
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uid[2] = FlashSendByte(0xFF);
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uid[1] = FlashSendByte(0xFF);
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uid[0] = FlashSendLastByte(0xFF);
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uid[2] = FlashSendByte(0xFF);
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uid[1] = FlashSendByte(0xFF);
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uid[0] = FlashSendLastByte(0xFF);
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}
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uint16_t Flash_ReadData(uint32_t address, uint8_t *out, uint16_t len) {
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if (!FlashInit()) return 0;
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if (!FlashInit()) return 0;
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// length should never be zero
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if (!len || Flash_CheckBusy(BUSY_TIMEOUT)) return 0;
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// length should never be zero
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if (!len || Flash_CheckBusy(BUSY_TIMEOUT)) return 0;
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uint8_t cmd = (FASTFLASH) ? FASTREAD : READDATA;
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FlashSendByte(cmd);
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Flash_TransferAdresse(address);
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FlashSendByte(cmd);
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Flash_TransferAdresse(address);
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if (FASTFLASH){
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FlashSendByte(DUMMYBYTE);
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}
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if (FASTFLASH){
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FlashSendByte(DUMMYBYTE);
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}
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uint16_t i = 0;
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for (; i < (len - 1); i++)
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out[i] = FlashSendByte(0xFF);
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uint16_t i = 0;
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for (; i < (len - 1); i++)
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out[i] = FlashSendByte(0xFF);
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out[i] = FlashSendLastByte(0xFF);
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FlashStop();
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return len;
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out[i] = FlashSendLastByte(0xFF);
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FlashStop();
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return len;
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}
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|
||||
void Flash_TransferAdresse(uint32_t address){
|
||||
FlashSendByte((address >> 16) & 0xFF);
|
||||
FlashSendByte((address >> 8) & 0xFF);
|
||||
FlashSendByte((address >> 0) & 0xFF);
|
||||
FlashSendByte((address >> 16) & 0xFF);
|
||||
FlashSendByte((address >> 8) & 0xFF);
|
||||
FlashSendByte((address >> 0) & 0xFF);
|
||||
}
|
||||
|
||||
/* This ensure we can ReadData without having to cycle through initialization everytime */
|
||||
uint16_t Flash_ReadDataCont(uint32_t address, uint8_t *out, uint16_t len) {
|
||||
|
||||
// length should never be zero
|
||||
if (!len) return 0;
|
||||
// length should never be zero
|
||||
if (!len) return 0;
|
||||
|
||||
uint8_t cmd = (FASTFLASH) ? FASTREAD : READDATA;
|
||||
|
||||
FlashSendByte(cmd);
|
||||
Flash_TransferAdresse(address);
|
||||
FlashSendByte(cmd);
|
||||
Flash_TransferAdresse(address);
|
||||
|
||||
if (FASTFLASH){
|
||||
FlashSendByte(DUMMYBYTE);
|
||||
}
|
||||
FlashSendByte(DUMMYBYTE);
|
||||
}
|
||||
|
||||
uint16_t i = 0;
|
||||
for (; i < (len - 1); i++)
|
||||
out[i] = FlashSendByte(0xFF);
|
||||
uint16_t i = 0;
|
||||
for (; i < (len - 1); i++)
|
||||
out[i] = FlashSendByte(0xFF);
|
||||
|
||||
out[i] = FlashSendLastByte(0xFF);
|
||||
return len;
|
||||
out[i] = FlashSendLastByte(0xFF);
|
||||
return len;
|
||||
}
|
||||
|
||||
|
||||
|
@ -307,89 +307,89 @@ uint16_t Flash_ReadDataCont(uint32_t address, uint8_t *out, uint16_t len) {
|
|||
// if len > 256, it might wrap around and overwrite pos 0.
|
||||
uint16_t Flash_WriteData(uint32_t address, uint8_t *in, uint16_t len) {
|
||||
|
||||
// length should never be zero
|
||||
if (!len)
|
||||
return 0;
|
||||
// length should never be zero
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
// Max 256 bytes write
|
||||
if (((address & 0xFF) + len) > 256) {
|
||||
Dbprintf("Flash_WriteData 256 fail [ 0x%02x ] [ %u ]", (address & 0xFF)+len, len );
|
||||
return 0;
|
||||
}
|
||||
// Max 256 bytes write
|
||||
if (((address & 0xFF) + len) > 256) {
|
||||
Dbprintf("Flash_WriteData 256 fail [ 0x%02x ] [ %u ]", (address & 0xFF)+len, len );
|
||||
return 0;
|
||||
}
|
||||
|
||||
// out-of-range
|
||||
if ( (( address >> 16 ) & 0xFF ) > MAX_BLOCKS) {
|
||||
Dbprintf("Flash_WriteData, block out-of-range");
|
||||
return 0;
|
||||
}
|
||||
// out-of-range
|
||||
if ( (( address >> 16 ) & 0xFF ) > MAX_BLOCKS) {
|
||||
Dbprintf("Flash_WriteData, block out-of-range");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!FlashInit()) {
|
||||
if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
|
||||
return 0;
|
||||
}
|
||||
if (!FlashInit()) {
|
||||
if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
|
||||
return 0;
|
||||
}
|
||||
|
||||
Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
|
||||
Flash_WriteEnable();
|
||||
Flash_WriteEnable();
|
||||
|
||||
FlashSendByte(PAGEPROG);
|
||||
FlashSendByte((address >> 16) & 0xFF);
|
||||
FlashSendByte((address >> 8) & 0xFF);
|
||||
FlashSendByte((address >> 0) & 0xFF);
|
||||
FlashSendByte(PAGEPROG);
|
||||
FlashSendByte((address >> 16) & 0xFF);
|
||||
FlashSendByte((address >> 8) & 0xFF);
|
||||
FlashSendByte((address >> 0) & 0xFF);
|
||||
|
||||
uint16_t i = 0;
|
||||
for (; i < (len - 1); i++)
|
||||
FlashSendByte(in[i]);
|
||||
uint16_t i = 0;
|
||||
for (; i < (len - 1); i++)
|
||||
FlashSendByte(in[i]);
|
||||
|
||||
FlashSendLastByte(in[i]);
|
||||
FlashSendLastByte(in[i]);
|
||||
|
||||
FlashStop();
|
||||
return len;
|
||||
FlashStop();
|
||||
return len;
|
||||
}
|
||||
|
||||
|
||||
// length should never be zero
|
||||
// Max 256 bytes write
|
||||
// Max 256 bytes write
|
||||
// out-of-range
|
||||
uint16_t Flash_WriteDataCont(uint32_t address, uint8_t *in, uint16_t len) {
|
||||
|
||||
if (!len)
|
||||
return 0;
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
if (((address & 0xFF) + len) > 256) {
|
||||
Dbprintf("Flash_WriteDataCont 256 fail [ 0x%02x ] [ %u ]", (address & 0xFF)+len, len );
|
||||
return 0;
|
||||
}
|
||||
if (((address & 0xFF) + len) > 256) {
|
||||
Dbprintf("Flash_WriteDataCont 256 fail [ 0x%02x ] [ %u ]", (address & 0xFF)+len, len );
|
||||
return 0;
|
||||
}
|
||||
|
||||
if ( (( address >> 16 ) & 0xFF ) > MAX_BLOCKS) {
|
||||
Dbprintf("Flash_WriteDataCont, block out-of-range");
|
||||
return 0;
|
||||
}
|
||||
if ( (( address >> 16 ) & 0xFF ) > MAX_BLOCKS) {
|
||||
Dbprintf("Flash_WriteDataCont, block out-of-range");
|
||||
return 0;
|
||||
}
|
||||
|
||||
FlashSendByte(PAGEPROG);
|
||||
FlashSendByte((address >> 16) & 0xFF);
|
||||
FlashSendByte((address >> 8) & 0xFF);
|
||||
FlashSendByte((address >> 0) & 0xFF);
|
||||
FlashSendByte(PAGEPROG);
|
||||
FlashSendByte((address >> 16) & 0xFF);
|
||||
FlashSendByte((address >> 8) & 0xFF);
|
||||
FlashSendByte((address >> 0) & 0xFF);
|
||||
|
||||
uint16_t i = 0;
|
||||
for (; i < (len - 1); i++)
|
||||
FlashSendByte(in[i]);
|
||||
uint16_t i = 0;
|
||||
for (; i < (len - 1); i++)
|
||||
FlashSendByte(in[i]);
|
||||
|
||||
FlashSendLastByte(in[i]);
|
||||
return len;
|
||||
FlashSendLastByte(in[i]);
|
||||
return len;
|
||||
}
|
||||
|
||||
// assumes valid start 256 based 00 address
|
||||
//
|
||||
uint16_t Flash_Write(uint32_t address, uint8_t *in, uint16_t len) {
|
||||
|
||||
bool isok;
|
||||
uint16_t res, bytes_sent = 0, bytes_remaining = len;
|
||||
bool isok;
|
||||
uint16_t res, bytes_sent = 0, bytes_remaining = len;
|
||||
uint8_t buf[FLASH_MEM_BLOCK_SIZE];
|
||||
while (bytes_remaining > 0) {
|
||||
|
||||
Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_WriteEnable();
|
||||
Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_WriteEnable();
|
||||
|
||||
uint32_t bytes_in_packet = MIN(FLASH_MEM_BLOCK_SIZE, bytes_remaining);
|
||||
|
||||
|
@ -397,85 +397,85 @@ uint16_t Flash_Write(uint32_t address, uint8_t *in, uint16_t len) {
|
|||
|
||||
res = Flash_WriteDataCont(address + bytes_sent, buf, bytes_in_packet);
|
||||
|
||||
bytes_remaining -= bytes_in_packet;
|
||||
bytes_remaining -= bytes_in_packet;
|
||||
bytes_sent += bytes_in_packet;
|
||||
|
||||
isok = (res == bytes_in_packet);
|
||||
|
||||
if (!isok)
|
||||
goto out;
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
FlashStop();
|
||||
return len;
|
||||
FlashStop();
|
||||
return len;
|
||||
}
|
||||
|
||||
|
||||
bool Flash_WipeMemoryPage(uint8_t page) {
|
||||
if (!FlashInit()) {
|
||||
if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
|
||||
return false;
|
||||
}
|
||||
Flash_ReadStat1();
|
||||
if (!FlashInit()) {
|
||||
if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
|
||||
return false;
|
||||
}
|
||||
Flash_ReadStat1();
|
||||
|
||||
// Each block is 64Kb. One block erase takes 1s ( 1000ms )
|
||||
Flash_WriteEnable(); Flash_Erase64k(page); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
// Each block is 64Kb. One block erase takes 1s ( 1000ms )
|
||||
Flash_WriteEnable(); Flash_Erase64k(page); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
|
||||
FlashStop();
|
||||
return true;
|
||||
FlashStop();
|
||||
return true;
|
||||
}
|
||||
// Wipes flash memory completely, fills with 0xFF
|
||||
bool Flash_WipeMemory() {
|
||||
if (!FlashInit()) {
|
||||
if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
|
||||
return false;
|
||||
}
|
||||
Flash_ReadStat1();
|
||||
if (!FlashInit()) {
|
||||
if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
|
||||
return false;
|
||||
}
|
||||
Flash_ReadStat1();
|
||||
|
||||
// Each block is 64Kb. Four blocks
|
||||
// one block erase takes 1s ( 1000ms )
|
||||
Flash_WriteEnable(); Flash_Erase64k(0); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_WriteEnable(); Flash_Erase64k(1); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_WriteEnable(); Flash_Erase64k(2); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_WriteEnable(); Flash_Erase64k(3); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
// Each block is 64Kb. Four blocks
|
||||
// one block erase takes 1s ( 1000ms )
|
||||
Flash_WriteEnable(); Flash_Erase64k(0); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_WriteEnable(); Flash_Erase64k(1); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_WriteEnable(); Flash_Erase64k(2); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
Flash_WriteEnable(); Flash_Erase64k(3); Flash_CheckBusy(BUSY_TIMEOUT);
|
||||
|
||||
FlashStop();
|
||||
return true;
|
||||
FlashStop();
|
||||
return true;
|
||||
}
|
||||
|
||||
// enable the flash write
|
||||
// enable the flash write
|
||||
void Flash_WriteEnable() {
|
||||
FlashSendLastByte(WRITEENABLE);
|
||||
if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash Write enabled");
|
||||
FlashSendLastByte(WRITEENABLE);
|
||||
if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash Write enabled");
|
||||
}
|
||||
|
||||
// erase 4K at one time
|
||||
// erase 4K at one time
|
||||
// execution time: 0.8ms / 800us
|
||||
bool Flash_Erase4k(uint8_t block, uint8_t sector) {
|
||||
|
||||
if (block > MAX_BLOCKS || sector > MAX_SECTORS) return false;
|
||||
if (block > MAX_BLOCKS || sector > MAX_SECTORS) return false;
|
||||
|
||||
FlashSendByte(SECTORERASE);
|
||||
FlashSendByte(block);
|
||||
FlashSendByte(sector << 4);
|
||||
FlashSendLastByte(00);
|
||||
return true;
|
||||
FlashSendByte(SECTORERASE);
|
||||
FlashSendByte(block);
|
||||
FlashSendByte(sector << 4);
|
||||
FlashSendLastByte(00);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
// erase 32K at one time
|
||||
// erase 32K at one time
|
||||
// execution time: 0,3s / 300ms
|
||||
bool Flash_Erase32k(uint32_t address) {
|
||||
if (address & (32*1024 - 1)) {
|
||||
if ( MF_DBGLEVEL > 1 ) Dbprintf("Flash_Erase32k : Address is not align at 4096");
|
||||
return false;
|
||||
}
|
||||
FlashSendByte(BLOCK32ERASE);
|
||||
FlashSendByte((address >> 16) & 0xFF);
|
||||
FlashSendByte((address >> 8) & 0xFF);
|
||||
FlashSendLastByte((address >> 0) & 0xFF);
|
||||
return true;
|
||||
if (address & (32*1024 - 1)) {
|
||||
if ( MF_DBGLEVEL > 1 ) Dbprintf("Flash_Erase32k : Address is not align at 4096");
|
||||
return false;
|
||||
}
|
||||
FlashSendByte(BLOCK32ERASE);
|
||||
FlashSendByte((address >> 16) & 0xFF);
|
||||
FlashSendByte((address >> 8) & 0xFF);
|
||||
FlashSendLastByte((address >> 0) & 0xFF);
|
||||
return true;
|
||||
}
|
||||
*/
|
||||
|
||||
|
@ -489,52 +489,52 @@ bool Flash_Erase32k(uint32_t address) {
|
|||
// 0x03 00 00 -- 0x 03 FF FF == block 3
|
||||
bool Flash_Erase64k(uint8_t block) {
|
||||
|
||||
if (block > MAX_BLOCKS) return false;
|
||||
if (block > MAX_BLOCKS) return false;
|
||||
|
||||
FlashSendByte(BLOCK64ERASE);
|
||||
FlashSendByte(block);
|
||||
FlashSendByte(0x00);
|
||||
FlashSendLastByte(0x00);
|
||||
return true;
|
||||
FlashSendByte(BLOCK64ERASE);
|
||||
FlashSendByte(block);
|
||||
FlashSendByte(0x00);
|
||||
FlashSendLastByte(0x00);
|
||||
return true;
|
||||
}
|
||||
|
||||
// Erase chip
|
||||
// Erase chip
|
||||
void Flash_EraseChip(void) {
|
||||
FlashSendLastByte(CHIPERASE);
|
||||
FlashSendLastByte(CHIPERASE);
|
||||
}
|
||||
|
||||
void Flashmem_print_status(void) {
|
||||
DbpString("Flash memory");
|
||||
Dbprintf(" Baudrate................%dMHz",FLASHMEM_SPIBAUDRATE/1000000);
|
||||
DbpString("Flash memory");
|
||||
Dbprintf(" Baudrate................%dMHz",FLASHMEM_SPIBAUDRATE/1000000);
|
||||
|
||||
if (!FlashInit()) {
|
||||
DbpString(" Init....................FAIL");
|
||||
return;
|
||||
}
|
||||
DbpString(" Init....................OK");
|
||||
if (!FlashInit()) {
|
||||
DbpString(" Init....................FAIL");
|
||||
return;
|
||||
}
|
||||
DbpString(" Init....................OK");
|
||||
|
||||
uint8_t dev_id = Flash_ReadID();
|
||||
switch (dev_id) {
|
||||
case 0x11 :
|
||||
DbpString(" Memory size.............2 mbits / 256kb");
|
||||
break;
|
||||
case 0x10 :
|
||||
DbpString(" Memory size..... .......1 mbits / 128kb");
|
||||
break;
|
||||
case 0x05 :
|
||||
DbpString(" Memory size.............512 kbits / 64kb");
|
||||
break;
|
||||
default :
|
||||
DbpString(" Device ID............... --> Unknown <--");
|
||||
break;
|
||||
}
|
||||
uint8_t dev_id = Flash_ReadID();
|
||||
switch (dev_id) {
|
||||
case 0x11 :
|
||||
DbpString(" Memory size.............2 mbits / 256kb");
|
||||
break;
|
||||
case 0x10 :
|
||||
DbpString(" Memory size..... .......1 mbits / 128kb");
|
||||
break;
|
||||
case 0x05 :
|
||||
DbpString(" Memory size.............512 kbits / 64kb");
|
||||
break;
|
||||
default :
|
||||
DbpString(" Device ID............... --> Unknown <--");
|
||||
break;
|
||||
}
|
||||
|
||||
uint8_t uid[8] = {0,0,0,0,0,0,0,0};
|
||||
Flash_UniqueID(uid);
|
||||
Dbprintf(" Unique ID...............0x%02x%02x%02x%02x%02x%02x%02x%02x",
|
||||
uid[7], uid[6], uid[5], uid[4],
|
||||
uid[3], uid[2], uid[1], uid[0]
|
||||
);
|
||||
uint8_t uid[8] = {0,0,0,0,0,0,0,0};
|
||||
Flash_UniqueID(uid);
|
||||
Dbprintf(" Unique ID...............0x%02x%02x%02x%02x%02x%02x%02x%02x",
|
||||
uid[7], uid[6], uid[5], uid[4],
|
||||
uid[3], uid[2], uid[1], uid[0]
|
||||
);
|
||||
|
||||
FlashStop();
|
||||
FlashStop();
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue