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Add thinfilm simulation
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01d1db8970
commit
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5 changed files with 180 additions and 2 deletions
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@ -36,3 +36,117 @@ void ReadThinFilm(void) {
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set_tracing(false);
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}
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#define SEC_D 0xf0
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#define SEC_E 0x0f
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#define SEC_F 0x00
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uint16_t FpgaSendQueueDelay;
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uint16_t ReadReaderField(void) {
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uint16_t hf_av = AvgAdc(ADC_CHAN_HF);
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if (((MAX_ADC_HF_VOLTAGE * hf_av) >> 10) > MAX_ADC_HF_VOLTAGE - 300)
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hf_av = AvgAdc(ADC_CHAN_HF_RDV40);
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return hf_av;
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}
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static void CodeThinfilmAsTag(const uint8_t *cmd, uint16_t len) {
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ToSendReset();
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for (uint16_t i = 0; i < len; i++) {
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uint8_t b = cmd[i];
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for (uint8_t j = 0; j < 8; j++) {
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ToSend[++ToSendMax] = b & 0x80 ? SEC_D : SEC_E;
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b <<= 1;
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}
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}
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ToSendMax++;
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}
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int EmSendCmdThinfilmRaw(uint8_t *resp, uint16_t respLen) {
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volatile uint8_t b;
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uint16_t i = 0;
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uint32_t ThisTransferTime;
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// wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
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for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
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while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
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if (AT91C_BASE_SSC->SSC_RHR) break;
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}
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while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
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// Clear TXRDY:
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AT91C_BASE_SSC->SSC_THR = SEC_F;
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// send cycle
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for (; i < respLen;) {
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
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AT91C_BASE_SSC->SSC_THR = resp[i++];
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FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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}
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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b = (uint16_t)(AT91C_BASE_SSC->SSC_RHR);
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(void)b;
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}
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if (BUTTON_PRESS()) break;
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}
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// Ensure that the FPGA Delay Queue is empty
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uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
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for (i = 0; i <= fpga_queued_bits / 8 + 1;) {
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
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AT91C_BASE_SSC->SSC_THR = SEC_F;
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FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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i++;
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}
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}
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return 0;
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}
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void SimulateThinFilm(uint8_t *data, size_t len) {
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Dbprintf("Simulate %i-bit Thinfilm tag", len * 8);
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Dbhexdump(len, data, true);
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int16_t status = PM3_SUCCESS;
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CodeThinfilmAsTag(data, len);
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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// Set up the synchronous serial port
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FpgaSetupSsc();
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// connect Demodulated Signal to ADC:
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
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SpinDelay(100);
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uint16_t hf_baseline = ReadReaderField();
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// Start the timer
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StartCountSspClk();
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bool reader_detected = false;
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LED_A_ON();
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for (;;) {
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WDT_HIT();
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if (BUTTON_PRESS() || data_available()) {
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status = PM3_EOPABORTED;
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break;
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}
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uint16_t hf_av = ReadReaderField();
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if (hf_av < hf_baseline)
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hf_baseline = hf_av;
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if (hf_av > hf_baseline + 10) {
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EmSendCmdThinfilmRaw(ToSend, ToSendMax);
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if (!reader_detected) {
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LED_B_ON();
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Dbprintf("Reader detected, start beaming data");
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reader_detected = true;
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}
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} else {
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if (reader_detected) {
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LED_B_OFF();
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Dbprintf("Reader gone, stop beaming data");
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reader_detected = false;
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}
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}
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}
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LED_A_OFF();
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reply_ng(CMD_SIMULATE_TAG_THINFILM, status, NULL, 0);
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}
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