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This commit is contained in:
Philippe Teuwen 2019-05-09 01:07:34 +02:00
commit 84f696451d
8 changed files with 17 additions and 17 deletions
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2
armsrc/iclass.c
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@ -1071,7 +1071,7 @@ static void CodeIClassTagAnswer(const uint8_t *cmd, int len) {
/*
* SOF comprises 3 parts;
* * An unmodulated time of 56.64 us
* * 24 pulses of 423.75 KHz (fc/32)
* * 24 pulses of 423.75 kHz (fc/32)
* * A logic 1, which starts with an unmodulated time of 18.88us
* followed by 8 pulses of 423.75kHz (fc/32)
*

2
armsrc/iso14443b.c
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@ -180,7 +180,7 @@ static void CodeIso14443bAsTag(const uint8_t *cmd, int len) {
* Reader to card | ASK - Amplitude Shift Keying Modulation (PCD to PICC for Type B) (NRZ-L encodig)
* Card to reader | BPSK - Binary Phase Shift Keying Modulation, (PICC to PCD for Type B)
*
* fc - carrier frequency 13.56mHz
* fc - carrier frequency 13.56 MHz
* TR0 - Guard Time per 14443-2
* TR1 - Synchronization Time per 14443-2
* TR2 - PICC to PCD Frame Delay Time (per 14443-3 Amendment 1)

6
armsrc/lfsampling.c
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@ -20,7 +20,7 @@ sample_config config = { 1, 8, 1, 95, 0 } ;
void printConfig() {
DbpString(_BLUE_("LF Sampling config"));
Dbprintf(" [q] divisor.............%d (%d KHz)", config.divisor, 12000 / (config.divisor + 1));
Dbprintf(" [q] divisor.............%d (%d kHz)", config.divisor, 12000 / (config.divisor + 1));
Dbprintf(" [b] bps.................%d", config.bits_per_sample);
Dbprintf(" [d] decimation..........%d", config.decimation);
Dbprintf(" [a] averaging...........%s", (config.averaging) ? "Yes" : "No");
@ -76,8 +76,8 @@ void pushBit(BitstreamOut *stream, uint8_t bit) {
/**
* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
* if not already loaded, sets divisor and starts up the antenna.
* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
* 0 or 95 ==> 125 KHz
* @param divisor : 1, 88> 255 or negative ==> 134.8 kHz
* 0 or 95 ==> 125 kHz
*
**/
void LFSetupFPGAForADC(int divisor, bool lf_field) {

4
armsrc/lfsampling.h
View file

@ -59,8 +59,8 @@ uint32_t DoAcquisition_config(bool silent, int sample_size);
/**
* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
* if not already loaded, sets divisor and starts up the antenna.
* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
* 0 or 95 ==> 125 KHz
* @param divisor : 1, 88> 255 or negative ==> 134.8 kHz
* 0 or 95 ==> 125 kHz
*
**/
void LFSetupFPGAForADC(int divisor, bool lf_field);

4
client/cmdhw.c
View file

@ -28,7 +28,7 @@ static int usage_hw_detectreader(void) {
PrintAndLogEx(NORMAL, "Usage: hw detectreader [h] <L|H>");
PrintAndLogEx(NORMAL, "Options:");
PrintAndLogEx(NORMAL, " h This help");
PrintAndLogEx(NORMAL, " <type> L = 125/134 kHz, H = 13.56 mHz");
PrintAndLogEx(NORMAL, " <type> L = 125/134 kHz, H = 13.56 MHz");
PrintAndLogEx(NORMAL, "");
PrintAndLogEx(NORMAL, "Examples:");
PrintAndLogEx(NORMAL, " hw detectreader L");
@ -418,7 +418,7 @@ static int CmdSetDivisor(const char *Cmd) {
// 12 000 000 (12Mhz)
clearCommandBuffer();
SendCommandMIX(CMD_SET_LF_DIVISOR, arg, 0, 0, NULL, 0);
PrintAndLogEx(SUCCESS, "Divisor set, expected %.1f KHz", ((double)12000 / (arg + 1)));
PrintAndLogEx(SUCCESS, "Divisor set, expected %.1f kHz", ((double)12000 / (arg + 1)));
return PM3_SUCCESS;
}

12
client/cmdlf.c
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@ -55,18 +55,18 @@ static int usage_lf_config(void) {
PrintAndLogEx(NORMAL, "Usage: lf config [h] [H|<divisor>] [b <bps>] [d <decim>] [a 0|1]");
PrintAndLogEx(NORMAL, "Options:");
PrintAndLogEx(NORMAL, " h This help");
PrintAndLogEx(NORMAL, " L Low frequency (125 KHz)");
PrintAndLogEx(NORMAL, " H High frequency (134 KHz)");
PrintAndLogEx(NORMAL, " q <divisor> Manually set divisor. 88-> 134KHz, 95-> 125 Hz");
PrintAndLogEx(NORMAL, " L Low frequency (125 kHz)");
PrintAndLogEx(NORMAL, " H High frequency (134 kHz)");
PrintAndLogEx(NORMAL, " q <divisor> Manually set divisor. 88-> 134 kHz, 95-> 125 kHz");
PrintAndLogEx(NORMAL, " b <bps> Sets resolution of bits per sample. Default (max): 8");
PrintAndLogEx(NORMAL, " d <decim> Sets decimation. A value of N saves only 1 in N samples. Default: 1");
PrintAndLogEx(NORMAL, " a [0|1] Averaging - if set, will average the stored sample value when decimating. Default: 1");
PrintAndLogEx(NORMAL, " t <threshold> Sets trigger threshold. 0 means no threshold (range: 0-128)");
PrintAndLogEx(NORMAL, "Examples:");
PrintAndLogEx(NORMAL, " lf config b 8 L");
PrintAndLogEx(NORMAL, " Samples at 125KHz, 8bps.");
PrintAndLogEx(NORMAL, " Samples at 125 kHz, 8bps.");
PrintAndLogEx(NORMAL, " lf config H b 4 d 3");
PrintAndLogEx(NORMAL, " Samples at 134KHz, averages three samples into one, stored with ");
PrintAndLogEx(NORMAL, " Samples at 134 kHz, averages three samples into one, stored with ");
PrintAndLogEx(NORMAL, " a resolution of 4 bits per sample.");
PrintAndLogEx(NORMAL, " lf read");
PrintAndLogEx(NORMAL, " Performs a read (active field)");
@ -919,7 +919,7 @@ int CmdLFfind(const char *Cmd) {
//if (demodFermax()) { PrintAndLogEx(SUCCESS, "\nValid " _GREEN_("Fermax ID") " found!"); goto out;}
//if (demodFlex()) { PrintAndLogEx(SUCCESS, "\nValid " _GREEN_("Flex ID") " found!"); goto out;}
PrintAndLogEx(FAILED, _RED_("No known 125/134 KHz tags found!"));
PrintAndLogEx(FAILED, _RED_("No known 125/134 kHz tags found!"));
if (testRaw == 'u') {
//test unknown tag formats (raw mode)

2
client/cmdsmartcard.c
View file

@ -751,7 +751,7 @@ static int CmdSmartInfo(const char *Cmd) {
if (Di && Fi) {
PrintAndLogEx(NORMAL, "\t- Cycles/ETU %d", Fi / Di);
PrintAndLogEx(NORMAL, "\t- %.1f bits/sec at 4MHz", (float)4000000 / (Fi / Di));
PrintAndLogEx(NORMAL, "\t- %.1f bits/sec at 4 MHz", (float)4000000 / (Fi / Di));
PrintAndLogEx(NORMAL, "\t- %.1f bits/sec at Fmax (%.1fMHz)", (F * 1000000) / (Fi / Di), F);
} else {
PrintAndLogEx(WARNING, "\t- Di or Fi is RFU.");

2
fpga/hi_simulate.v
View file

@ -63,7 +63,7 @@ reg ssp_clk;
always @(negedge adc_clk)
begin
if(mod_type == 3'b101)
// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
// Get bit every at 53kHz (every 8th carrier bit of 424kHz)
ssp_clk <= ssp_clk_divider[7];
else if(mod_type == 3'b010)
// Get next bit at 212kHz