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This commit is contained in:
Philippe Teuwen 2019-08-13 17:51:11 +02:00
commit 847b6bcc33
5 changed files with 27 additions and 22 deletions
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14
fpga/fpga_lf.v
View file

@ -102,13 +102,13 @@ lo_edge_detect le(
);
lo_adc la(
pck0,
la_pwr_lo, la_pwr_hi, la_pwr_oe1, la_pwr_oe2, la_pwr_oe3, la_pwr_oe4,
adc_d, la_adc_clk,
la_ssp_frame, la_ssp_din, ssp_dout, la_ssp_clk,
cross_hi, cross_lo,
la_dbg, divisor,
lo_is_125khz, lf_field
pck0,
la_pwr_lo, la_pwr_hi, la_pwr_oe1, la_pwr_oe2, la_pwr_oe3, la_pwr_oe4,
adc_d, la_adc_clk,
la_ssp_frame, la_ssp_din, ssp_dout, la_ssp_clk,
cross_hi, cross_lo,
la_dbg, divisor,
lo_is_125khz, lf_field
);
// Major modes:

20
fpga/lo_adc.v
View file

@ -55,28 +55,28 @@ assign ssp_frame = (pck_divider[7:3] == 5'd1) && !clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state)
if((pck_divider == 8'd7) && !clk_state)
begin
to_arm_shiftreg <= adc_d;
end
else
begin
begin
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
to_arm_shiftreg[0] <= 1'b0;
end
end
end
endmodule