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hitagS sim: fix timing of receive

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probably a regression from timer changes in 911766b
This commit is contained in:
Ember 'n0emis' Keske 2024-10-27 13:17:42 +01:00
commit 843bb46705
1 changed files with 4 additions and 4 deletions
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8
armsrc/hitagS.c
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@ -769,7 +769,7 @@ void hts_simulate(bool tag_mem_supplied, const uint8_t *data, bool ledcontrol) {
if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) { if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
// Retrieve the new timing values // Retrieve the new timing values
int ra = (AT91C_BASE_TC1->TC_RA / T0) + overflow; int rb = (AT91C_BASE_TC1->TC_RB / T0) + overflow;
overflow = 0; overflow = 0;
// Reset timer every frame, we have to capture the last edge for timing // Reset timer every frame, we have to capture the last edge for timing
@ -780,15 +780,15 @@ void hts_simulate(bool tag_mem_supplied, const uint8_t *data, bool ledcontrol) {
if (start_time == 0) start_time = TIMESTAMP - HITAG_T_LOW; if (start_time == 0) start_time = TIMESTAMP - HITAG_T_LOW;
// Capture reader frame // Capture reader frame
if (ra >= HITAG_T_STOP) { if (rb >= HITAG_T_STOP) {
if (rxlen != 0) { if (rxlen != 0) {
//DbpString("weird0?"); //DbpString("weird0?");
} }
} else if (ra >= HITAG_T_1_MIN) { } else if (rb >= HITAG_T_1_MIN) {
// '1' bit // '1' bit
rx[rxlen / 8] |= 1 << (7 - (rxlen % 8)); rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
rxlen++; rxlen++;
} else if (ra >= HITAG_T_0_MIN) { } else if (rb >= HITAG_T_0_MIN) {
// '0' bit // '0' bit
rx[rxlen / 8] |= 0 << (7 - (rxlen % 8)); rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
rxlen++; rxlen++;