change: fixed xcorrelation for strong signal

The initial code assumed phase shift modulation only. Lately,
xcorrelation is also used for load modulation. But the initial
the assumption that 11 bits are enough isn't true for load
modulation.

This change extends the registers by 2 bits and compresses the
uper bits to preserve the sensitivity on the lower end.
This commit is contained in:
Andreas Dröscher 2018-08-10 00:49:43 +02:00
commit 83a4259ddc
2 changed files with 41 additions and 18 deletions

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@ -72,15 +72,21 @@ end
// Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples, // Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,
// so we need a 6-bit counter. // so we need a 6-bit counter.
reg [5:0] corr_i_cnt; reg [5:0] corr_i_cnt;
// And a couple of registers in which to accumulate the correlations.
// We would add at most 32 times the difference between unmodulated and modulated signal. It should // And a couple of registers in which to accumulate the correlations. Since
// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%. // load modulation saturates the ADC we have to use a large enough register
// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign. // 32 * 255 = 8160, which can be held in 13 bits. Add 1 bit for sign.
reg signed [11:0] corr_i_accum; //
reg signed [11:0] corr_q_accum; // The initial code assumed a phase shift of up to 25% and the accumulators were
// 11 bits (32 * 255 * 0,25 = 2040), we will pack all bits exceeding 11 bits into
// MSB. This prevents under/-overflows but preserves sensitivity on the lower end.
reg signed [13:0] corr_i_accum;
reg signed [13:0] corr_q_accum;
// we will report maximum 8 significant bits // we will report maximum 8 significant bits
reg signed [7:0] corr_i_out; reg signed [7:0] corr_i_out;
reg signed [7:0] corr_q_out; reg signed [7:0] corr_q_out;
// clock and frame signal for communication to ARM // clock and frame signal for communication to ARM
reg ssp_clk; reg ssp_clk;
reg ssp_frame; reg ssp_frame;
@ -100,19 +106,36 @@ begin
// send out later over the SSP. // send out later over the SSP.
if(corr_i_cnt == 6'd0) if(corr_i_cnt == 6'd0)
begin begin
// send 10 bits of tag signal, 4 MSBs are stuffed into 2 MSB
if(~corr_i_accum[13])
corr_i_out <= {corr_i_accum[13],
corr_i_accum[12] | corr_i_accum[11] | corr_i_accum[10],
corr_i_accum[12] | corr_i_accum[11] | corr_i_accum[9],
corr_i_accum[8:4]};
else
corr_i_out <= {corr_i_accum[13],
corr_i_accum[12] & corr_i_accum[11] & corr_i_accum[10],
corr_i_accum[12] & corr_i_accum[11] & corr_i_accum[9],
corr_i_accum[8:4]};
if(~corr_q_accum[13])
corr_q_out <= {corr_q_accum[13],
corr_q_accum[12] | corr_q_accum[11] | corr_q_accum[10],
corr_q_accum[12] | corr_q_accum[11] | corr_q_accum[9],
corr_q_accum[8:4]};
else
corr_q_out <= {corr_q_accum[13],
corr_q_accum[12] & corr_q_accum[11] & corr_q_accum[10],
corr_q_accum[12] & corr_q_accum[11] & corr_q_accum[9],
corr_q_accum[8:4]};
if(snoop) if(snoop)
begin begin
// Send 7 most significant bits of tag signal (signed), plus 1 bit reader signal // replace LSB with 1 bit reader signal
corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev}; corr_i_out[0] <= after_hysteresis_prev_prev;
corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev}; corr_q_out[0] <= after_hysteresis_prev;
after_hysteresis_prev_prev <= after_hysteresis; after_hysteresis_prev_prev <= after_hysteresis;
end end
else
begin
// 8 bits of tag signal
corr_i_out <= corr_i_accum[11:4];
corr_q_out <= corr_q_accum[11:4];
end
corr_i_accum <= adc_d; corr_i_accum <= adc_d;
corr_q_accum <= adc_d; corr_q_accum <= adc_d;