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812d9cc46a
5 changed files with 44 additions and 44 deletions
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@ -2021,11 +2021,11 @@ int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen) {
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while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
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b = AT91C_BASE_SSC->SSC_RHR;
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(void) b;
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/*
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/*
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while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY));
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b = AT91C_BASE_SSC->SSC_THR;
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(void) b;
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*/
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*/
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// wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
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for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
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@ -2045,7 +2045,7 @@ int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen) {
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FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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}
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/*
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/*
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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b = (uint16_t)(AT91C_BASE_SSC->SSC_RHR);
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(void)b;
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@ -394,8 +394,8 @@ static int CmdFdxClone(const char *Cmd) {
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PrintAndLogEx(INFO, " Country code %"PRIu32, country_code);
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PrintAndLogEx(INFO, " National code %"PRIu64, national_code);
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PrintAndLogEx(INFO, " Set animal bit %c", (is_animal) ? 'Y':'N');
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PrintAndLogEx(INFO, "Set data block bit %c", (has_extended) ? 'Y':'N');
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PrintAndLogEx(INFO, " Set animal bit %c", (is_animal) ? 'Y' : 'N');
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PrintAndLogEx(INFO, "Set data block bit %c", (has_extended) ? 'Y' : 'N');
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PrintAndLogEx(INFO, " Extended data 0x%"PRIX32, extended);
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PrintAndLogEx(INFO, " RFU 0");
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@ -474,8 +474,8 @@ static int CmdFdxSim(const char *Cmd) {
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PrintAndLogEx(INFO, " Country code %"PRIu32, country_code);
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PrintAndLogEx(INFO, " National code %"PRIu64, national_code);
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PrintAndLogEx(INFO, " Set animal bit %c", (is_animal) ? 'Y':'N');
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PrintAndLogEx(INFO, "Set data block bit %c", (has_extended) ? 'Y':'N');
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PrintAndLogEx(INFO, " Set animal bit %c", (is_animal) ? 'Y' : 'N');
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PrintAndLogEx(INFO, "Set data block bit %c", (has_extended) ? 'Y' : 'N');
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PrintAndLogEx(INFO, " Extended data 0x%"PRIX32, extended);
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PrintAndLogEx(INFO, " RFU 0");
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