From 762c942e953b8f2694fb919f1e7b924f8808f646 Mon Sep 17 00:00:00 2001 From: Alex Date: Tue, 29 Aug 2023 11:26:43 +0200 Subject: [PATCH] Redundant check A 3 bit counter will naturally roll over to zero on overflow, there is no need to explicitly check for max value and manually reset to zero --- fpga/hi_sniffer.v | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/fpga/hi_sniffer.v b/fpga/hi_sniffer.v index 11781ca5a..8cfb0fe9a 100644 --- a/fpga/hi_sniffer.v +++ b/fpga/hi_sniffer.v @@ -48,10 +48,7 @@ assign ssp_din = adc_d_out[0]; always @(posedge ssp_clk) begin - if(ssp_cnt[2:0] == 3'd7) - ssp_cnt[2:0] <= 3'd0; - else - ssp_cnt <= ssp_cnt + 1; + ssp_cnt <= ssp_cnt + 1; if(ssp_cnt[2:0] == 3'b000) // set frame length begin