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This commit is contained in:
Philippe Teuwen 2021-09-05 00:49:57 +02:00
commit 7404695e46
9 changed files with 290 additions and 290 deletions
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2
Makefile
View file

@ -292,7 +292,7 @@ else
@echo "Files with tabs: (rerun with EDIT=1 if you want to convert them with vim)" @echo "Files with tabs: (rerun with EDIT=1 if you want to convert them with vim)"
endif endif
# to remove tabs within lines, one can try with: vi $file -c ':set tabstop=4' -c ':set et|retab' -c ':wq' # to remove tabs within lines, one can try with: vi $file -c ':set tabstop=4' -c ':set et|retab' -c ':wq'
@find . \( -not -path "./cov-int/*" -and -not -path "./client/deps/*" -and \( -name "*.[ch]" -or \( -name "*.cpp" -and -not -name "*.moc.cpp" \) -or -name "*.lua" -or -name "*.py" -or -name "*.pl" -or -name "*.md" -or -name "*.txt" -or -name "*.awk" -or -name "*.v" -or -name "pm3" \) \) \ @find . \( -not -path "./cov-int/*" -and -not -path "./client/deps/*" -and -not -wholename "./client/src/pm3_*wrap.c" -and \( -name "*.[ch]" -or \( -name "*.cpp" -and -not -name "*.moc.cpp" \) -or -name "*.lua" -or -name "*.py" -or -name "*.pl" -or -name "*.md" -or -name "*.txt" -or -name "*.awk" -or -name "*.v" -or -name "pm3" \) \) \
-exec sh -c "$(TABSCMD)" \; -exec sh -c "$(TABSCMD)" \;
# @echo "Files with printf \\\\t:" # @echo "Files with printf \\\\t:"
# @find . \( -name "*.[ch]" -or \( -name "*.cpp" -and -not -name "*.moc.cpp" \) -or -name "*.lua" -or -name "*.py" -or -name "*.pl" -or -name "*.md" -or -name "*.txt" -or -name "*.awk" -or -name "*.v" \) \ # @find . \( -name "*.[ch]" -or \( -name "*.cpp" -and -not -name "*.moc.cpp" \) -or -name "*.lua" -or -name "*.py" -or -name "*.pl" -or -name "*.md" -or -name "*.txt" -or -name "*.awk" -or -name "*.v" \) \

2
armsrc/Standalone/lf_hidfcbrute.c
View file

@ -120,7 +120,7 @@ void RunMod(void) {
/* /*
int button_pressed = BUTTON_HELD(1000); // 1 second int button_pressed = BUTTON_HELD(1000); // 1 second
if (button_pressed == BUTTON_HOLD) { if (button_pressed == BUTTON_HOLD) {
break; break;
} }
*/ */
// If a user pressed the button once, briefly, output the current FC to the log file // If a user pressed the button once, briefly, output the current FC to the log file

52
fpga-xc3s100e/fpga_allinone.v
View file

@ -26,8 +26,8 @@ module fpga_hf(
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk, output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo, input cross_hi, input cross_lo,
output dbg, output dbg,
output PWR_LO_EN, output PWR_LO_EN,
input FPGA_SWITCH input FPGA_SWITCH
); );
@ -51,31 +51,31 @@ fpga_lfmod lfmod(
lfssp_frame, lfssp_din, lfssp_dout, lfssp_clk, lfssp_frame, lfssp_din, lfssp_dout, lfssp_clk,
lfcross_hi, lfcross_lo, lfcross_hi, lfcross_lo,
lfdbg, lfdbg,
lfPWR_LO_EN lfPWR_LO_EN
); );
mux2_oneout mux_spck_all (FPGA_SWITCH, spck, hfspck, lfspck); mux2_oneout mux_spck_all (FPGA_SWITCH, spck, hfspck, lfspck);
mux2_one mux_miso_all (FPGA_SWITCH, miso, hfmiso, lfmiso); mux2_one mux_miso_all (FPGA_SWITCH, miso, hfmiso, lfmiso);
mux2_oneout mux_mosi_all (FPGA_SWITCH, mosi, hfmosi, lfmosi); mux2_oneout mux_mosi_all (FPGA_SWITCH, mosi, hfmosi, lfmosi);
mux2_oneout mux_ncs_all (FPGA_SWITCH, ncs, hfncs, lfncs); mux2_oneout mux_ncs_all (FPGA_SWITCH, ncs, hfncs, lfncs);
mux2_oneout mux_pck0_all (FPGA_SWITCH, pck0, hfpck0, lfpck0); mux2_oneout mux_pck0_all (FPGA_SWITCH, pck0, hfpck0, lfpck0);
mux2_oneout mux_ck_1356meg_all (FPGA_SWITCH, ck_1356meg, hfck_1356meg, lfck_1356meg); mux2_oneout mux_ck_1356meg_all (FPGA_SWITCH, ck_1356meg, hfck_1356meg, lfck_1356meg);
mux2_oneout mux_ck_1356megb_all (FPGA_SWITCH, ck_1356megb, hfck_1356megb, lfck_1356megb); mux2_oneout mux_ck_1356megb_all (FPGA_SWITCH, ck_1356megb, hfck_1356megb, lfck_1356megb);
mux2_one mux_pwr_lo_all (FPGA_SWITCH, pwr_lo, hfpwr_lo, lfpwr_lo); mux2_one mux_pwr_lo_all (FPGA_SWITCH, pwr_lo, hfpwr_lo, lfpwr_lo);
mux2_one mux_pwr_hi_all (FPGA_SWITCH, pwr_hi, hfpwr_hi, lfpwr_hi); mux2_one mux_pwr_hi_all (FPGA_SWITCH, pwr_hi, hfpwr_hi, lfpwr_hi);
mux2_one mux_pwr_oe1_all (FPGA_SWITCH, pwr_oe1, hfpwr_oe1, lfpwr_oe1); mux2_one mux_pwr_oe1_all (FPGA_SWITCH, pwr_oe1, hfpwr_oe1, lfpwr_oe1);
mux2_one mux_pwr_oe2_all (FPGA_SWITCH, pwr_oe2, hfpwr_oe2, lfpwr_oe2); mux2_one mux_pwr_oe2_all (FPGA_SWITCH, pwr_oe2, hfpwr_oe2, lfpwr_oe2);
mux2_one mux_pwr_oe3_all (FPGA_SWITCH, pwr_oe3, hfpwr_oe3, lfpwr_oe3); mux2_one mux_pwr_oe3_all (FPGA_SWITCH, pwr_oe3, hfpwr_oe3, lfpwr_oe3);
mux2_one mux_pwr_oe4_all (FPGA_SWITCH, pwr_oe4, hfpwr_oe4, lfpwr_oe4); mux2_one mux_pwr_oe4_all (FPGA_SWITCH, pwr_oe4, hfpwr_oe4, lfpwr_oe4);
mux2_one mux_adc_clk_all (FPGA_SWITCH, adc_clk, hfadc_clk, lfadc_clk); mux2_one mux_adc_clk_all (FPGA_SWITCH, adc_clk, hfadc_clk, lfadc_clk);
mux2_one mux_adc_noe_all (FPGA_SWITCH, adc_noe, adc_noe, lfadc_noe); mux2_one mux_adc_noe_all (FPGA_SWITCH, adc_noe, adc_noe, lfadc_noe);
mux2_one mux_ssp_frame_all (FPGA_SWITCH, ssp_frame, hfssp_frame, lfssp_frame); mux2_one mux_ssp_frame_all (FPGA_SWITCH, ssp_frame, hfssp_frame, lfssp_frame);
mux2_one mux_ssp_din_all (FPGA_SWITCH, ssp_din, hfssp_din, lfssp_din); mux2_one mux_ssp_din_all (FPGA_SWITCH, ssp_din, hfssp_din, lfssp_din);
mux2_oneout mux_ssp_dout_all (FPGA_SWITCH, ssp_dout, hfssp_dout, lfssp_dout); mux2_oneout mux_ssp_dout_all (FPGA_SWITCH, ssp_dout, hfssp_dout, lfssp_dout);
mux2_one mux_ssp_clk_all (FPGA_SWITCH, ssp_clk, hfssp_clk, lfssp_clk); mux2_one mux_ssp_clk_all (FPGA_SWITCH, ssp_clk, hfssp_clk, lfssp_clk);
mux2_oneout mux_cross_hi_all (FPGA_SWITCH, cross_hi, hfcross_hi, lfcross_hi); mux2_oneout mux_cross_hi_all (FPGA_SWITCH, cross_hi, hfcross_hi, lfcross_hi);
mux2_oneout mux_cross_lo_all (FPGA_SWITCH, cross_lo, hfcross_lo, lfcross_lo); mux2_oneout mux_cross_lo_all (FPGA_SWITCH, cross_lo, hfcross_lo, lfcross_lo);
mux2_one mux_dbg_all (FPGA_SWITCH, dbg, hfdbg, lfdbg); mux2_one mux_dbg_all (FPGA_SWITCH, dbg, hfdbg, lfdbg);
mux2_one mux_PWR_LO_EN_all (FPGA_SWITCH, PWR_LO_EN, 1'b0, lfPWR_LO_EN); mux2_one mux_PWR_LO_EN_all (FPGA_SWITCH, PWR_LO_EN, 1'b0, lfPWR_LO_EN);
endmodule endmodule

26
fpga-xc3s100e/fpga_hfmod.v
View file

@ -108,32 +108,32 @@ wire [3:0] minor_mode = conf_word[3:0];
// 000 - HF reader // 000 - HF reader
hi_reader hr( hi_reader hr(
ck_1356megb, ck_1356megb,
hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4, hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
adc_d, hr_adc_clk, adc_d, hr_adc_clk,
hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk, hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
hr_dbg, hr_dbg,
subcarrier_frequency, minor_mode subcarrier_frequency, minor_mode
); );
// 001 - HF simulated tag // 001 - HF simulated tag
hi_simulate hs( hi_simulate hs(
ck_1356meg, ck_1356meg,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4, hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk, adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk, hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
hs_dbg, hs_dbg,
minor_mode minor_mode
); );
// 010 - HF ISO14443-A // 010 - HF ISO14443-A
hi_iso14443a hisn( hi_iso14443a hisn(
ck_1356meg, ck_1356meg,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4, hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk, adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk, hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
hisn_dbg, hisn_dbg,
minor_mode minor_mode
); );
// 011 - HF sniff // 011 - HF sniff
@ -158,9 +158,9 @@ hi_flite hfl(
// 101 - HF get trace // 101 - HF get trace
hi_get_trace gt( hi_get_trace gt(
ck_1356megb, ck_1356megb,
adc_d, trace_enable, major_mode, adc_d, trace_enable, major_mode,
gt_ssp_frame, gt_ssp_din, gt_ssp_clk gt_ssp_frame, gt_ssp_din, gt_ssp_clk
); );
// Major modes: // Major modes:

4
fpga-xc3s100e/fpga_lfmod.v
View file

@ -42,7 +42,7 @@ module fpga_lfmod(
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk, output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo, input cross_hi, input cross_lo,
output dbg, output dbg,
output PWR_LO_EN output PWR_LO_EN
); );
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
@ -228,7 +228,7 @@ mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, la_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0); mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, la_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, la_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0); mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, la_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, la_dbg, 1'b0, 1'b0, 1'b0, 1'b0); mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, la_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ant (major_mode, PWR_LO_EN, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0); mux8 mux_ant (major_mode, PWR_LO_EN, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled. // In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0; assign adc_noe = 1'b0;

176
fpga-xc3s100e/hi_get_trace.v
View file

@ -12,25 +12,25 @@ module hi_get_trace(
); );
input ck_1356megb; input ck_1356megb;
input [7:0] adc_d; input [7:0] adc_d;
input trace_enable; input trace_enable;
input [2:0] major_mode; input [2:0] major_mode;
output ssp_frame, ssp_din, ssp_clk; output ssp_frame, ssp_din, ssp_clk;
// clock divider // clock divider
reg [6:0] clock_cnt; reg [6:0] clock_cnt;
always @(negedge ck_1356megb) always @(negedge ck_1356megb)
begin begin
clock_cnt <= clock_cnt + 1; clock_cnt <= clock_cnt + 1;
end end
// sample at 13,56MHz / 8. The highest signal frequency (subcarrier) is 848,5kHz, i.e. in this case we oversample by a factor of 2 // sample at 13,56MHz / 8. The highest signal frequency (subcarrier) is 848,5kHz, i.e. in this case we oversample by a factor of 2
reg [2:0] sample_clock; reg [2:0] sample_clock;
always @(negedge ck_1356megb) always @(negedge ck_1356megb)
begin begin
if (sample_clock == 3'd7) if (sample_clock == 3'd7)
sample_clock <= 3'd0; sample_clock <= 3'd0;
else else
sample_clock <= sample_clock + 1; sample_clock <= sample_clock + 1;
end end
@ -41,65 +41,65 @@ reg write_enable1;
reg write_enable2; reg write_enable2;
always @(negedge ck_1356megb) always @(negedge ck_1356megb)
begin begin
previous_major_mode <= major_mode; previous_major_mode <= major_mode;
if (major_mode == `FPGA_MAJOR_MODE_HF_GET_TRACE) if (major_mode == `FPGA_MAJOR_MODE_HF_GET_TRACE)
begin begin
write_enable1 <= 1'b0; write_enable1 <= 1'b0;
write_enable2 <= 1'b0; write_enable2 <= 1'b0;
if (previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched into GET_TRACE mode if (previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched into GET_TRACE mode
addr <= start_addr; addr <= start_addr;
if (clock_cnt == 7'd0) if (clock_cnt == 7'd0)
begin begin
if (addr == 12'd3071) if (addr == 12'd3071)
addr <= 12'd0; addr <= 12'd0;
else else
addr <= addr + 1; addr <= addr + 1;
end end
end end
else if (major_mode != `FPGA_MAJOR_MODE_OFF) else if (major_mode != `FPGA_MAJOR_MODE_OFF)
begin begin
if (trace_enable) if (trace_enable)
begin begin
if (addr[11] == 1'b0) if (addr[11] == 1'b0)
begin begin
write_enable1 <= 1'b1; write_enable1 <= 1'b1;
write_enable2 <= 1'b0; write_enable2 <= 1'b0;
end end
else else
begin begin
write_enable1 <= 1'b0; write_enable1 <= 1'b0;
write_enable2 <= 1'b1; write_enable2 <= 1'b1;
end end
if (sample_clock == 3'b000) if (sample_clock == 3'b000)
begin begin
if (addr == 12'd3071) if (addr == 12'd3071)
begin
addr <= 12'd0;
write_enable1 <= 1'b1;
write_enable2 <= 1'b0;
end
else
begin
addr <= addr + 1;
end
end
end
else
begin
write_enable1 <= 1'b0;
write_enable2 <= 1'b0;
start_addr <= addr;
end
end
else // major_mode == `FPGA_MAJOR_MODE_OFF
begin
write_enable1 <= 1'b0;
write_enable2 <= 1'b0;
if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
begin begin
start_addr <= addr; addr <= 12'd0;
write_enable1 <= 1'b1;
write_enable2 <= 1'b0;
end end
end else
begin
addr <= addr + 1;
end
end
end
else
begin
write_enable1 <= 1'b0;
write_enable2 <= 1'b0;
start_addr <= addr;
end
end
else // major_mode == `FPGA_MAJOR_MODE_OFF
begin
write_enable1 <= 1'b0;
write_enable2 <= 1'b0;
if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
begin
start_addr <= addr;
end
end
end end
@ -110,20 +110,20 @@ reg [7:0] ram2 [1023:0]; // 1024 u8
always @(negedge ck_1356megb) always @(negedge ck_1356megb)
begin begin
if (write_enable1) if (write_enable1)
begin begin
ram1[addr[10:0]] <= adc_d; ram1[addr[10:0]] <= adc_d;
D_out1 <= adc_d; D_out1 <= adc_d;
end end
else else
D_out1 <= ram1[addr[10:0]]; D_out1 <= ram1[addr[10:0]];
if (write_enable2) if (write_enable2)
begin begin
ram2[addr[9:0]] <= adc_d; ram2[addr[9:0]] <= adc_d;
D_out2 <= adc_d; D_out2 <= adc_d;
end end
else else
D_out2 <= ram2[addr[9:0]]; D_out2 <= ram2[addr[9:0]];
end end
@ -135,27 +135,27 @@ reg [7:0] shift_out;
always @(negedge ck_1356megb) always @(negedge ck_1356megb)
begin begin
if (clock_cnt[3:0] == 4'd0) // update shift register every 16 clock cycles if (clock_cnt[3:0] == 4'd0) // update shift register every 16 clock cycles
begin begin
if (clock_cnt[6:4] == 3'd0) // either load new value if (clock_cnt[6:4] == 3'd0) // either load new value
begin begin
if (addr[11] == 1'b0) if (addr[11] == 1'b0)
shift_out <= D_out1; shift_out <= D_out1;
else else
shift_out <= D_out2; shift_out <= D_out2;
end end
else else
begin begin
// or shift left // or shift left
shift_out[7:1] <= shift_out[6:0]; shift_out[7:1] <= shift_out[6:0];
end end
end end
ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz
if (clock_cnt[6:4] == 3'b000) // set ssp_frame for 0...31 if (clock_cnt[6:4] == 3'b000) // set ssp_frame for 0...31
ssp_frame <= 1'b1; ssp_frame <= 1'b1;
else else
ssp_frame <= 1'b0; ssp_frame <= 1'b0;
end end

62
fpga-xc3s100e/hi_iso14443a.v
View file

@ -142,7 +142,7 @@ begin
end end
// adjust internal timer counter if necessary: // adjust internal timer counter if necessary:
if (negedge_cnt[3:0] == 4'd13 && (mod_type == `FPGA_HF_ISO14443A_SNIFFER || mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN) && deep_modulation) if (negedge_cnt[3:0] == 4'd13 && (mod_type == `FPGA_HF_ISO14443A_SNIFFER || mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN) && deep_modulation)
begin begin
if (reader_falling_edge_time == 4'd1) // reader signal changes right after sampling. Better sample earlier next time. if (reader_falling_edge_time == 4'd1) // reader signal changes right after sampling. Better sample earlier next time.
begin begin
@ -176,7 +176,7 @@ reg [3:0] mod_detect_reset_time;
always @(negedge adc_clk) always @(negedge adc_clk)
begin begin
if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN) if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
// (our) reader signal changes at negedge_cnt[3:0]=9, tag response expected to start n*16+4 ticks later, further delayed by // (our) reader signal changes at negedge_cnt[3:0]=9, tag response expected to start n*16+4 ticks later, further delayed by
// 3 ticks ADC conversion. The maximum filter output (edge detected) will be detected after subcarrier zero crossing (+7 ticks). // 3 ticks ADC conversion. The maximum filter output (edge detected) will be detected after subcarrier zero crossing (+7 ticks).
// To allow some timing variances, we want to have the maximum filter outputs well within the detection window, i.e. // To allow some timing variances, we want to have the maximum filter outputs well within the detection window, i.e.
@ -186,7 +186,7 @@ begin
mod_detect_reset_time <= 4'd4; mod_detect_reset_time <= 4'd4;
end end
else else
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER) if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
begin begin
// detect a rising edge of reader's signal and sync modulation detector to the tag's answer: // detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
if (~pre_after_hysteresis && after_hysteresis && deep_modulation) if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
@ -216,22 +216,22 @@ always @(negedge adc_clk)
begin begin
if(negedge_cnt[3:0] == mod_detect_reset_time) if(negedge_cnt[3:0] == mod_detect_reset_time)
begin begin
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER) if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
begin begin
// detect modulation signal: if modulating, there must have been a falling AND a rising edge // detect modulation signal: if modulating, there must have been a falling AND a rising edge
if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLDHIGH) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLDHIGH)) if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLDHIGH) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLDHIGH))
curbit <= 1'b1; // modulation curbit <= 1'b1; // modulation
else else
curbit <= 1'b0; // no modulation curbit <= 1'b0; // no modulation
end end
else else
begin begin
// detect modulation signal: if modulating, there must have been a falling AND a rising edge // detect modulation signal: if modulating, there must have been a falling AND a rising edge
if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD)) if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD))
curbit <= 1'b1; // modulation curbit <= 1'b1; // modulation
else else
curbit <= 1'b0; // no modulation curbit <= 1'b0; // no modulation
end end
// reset modulation detector // reset modulation detector
rx_mod_rising_edge_max <= 0; rx_mod_rising_edge_max <= 0;
rx_mod_falling_edge_max <= 0; rx_mod_falling_edge_max <= 0;
@ -366,7 +366,7 @@ reg mod_sig_coil;
always @(negedge adc_clk) always @(negedge adc_clk)
begin begin
if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD) // need to take care of proper fdt timing if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD) // need to take care of proper fdt timing
begin begin
if(fdt_counter == `FDT_COUNT) if(fdt_counter == `FDT_COUNT)
begin begin
@ -441,7 +441,7 @@ always @(negedge adc_clk)
begin begin
if (negedge_cnt[5:0] == 6'd63) // fill the buffer if (negedge_cnt[5:0] == 6'd63) // fill the buffer
begin begin
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER) if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
begin begin
if(deep_modulation) // a reader is sending (or there's no field at all) if(deep_modulation) // a reader is sending (or there's no field at all)
begin begin
@ -458,7 +458,7 @@ begin
end end
end end
if(negedge_cnt[2:0] == 3'b000 && mod_type == `FPGA_HF_ISO14443A_SNIFFER) // shift at double speed if(negedge_cnt[2:0] == 3'b000 && mod_type == `FPGA_HF_ISO14443A_SNIFFER) // shift at double speed
begin begin
// Don't shift if we just loaded new data, obviously. // Don't shift if we just loaded new data, obviously.
if(negedge_cnt[5:0] != 6'd0) if(negedge_cnt[5:0] != 6'd0)
@ -467,7 +467,7 @@ begin
end end
end end
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `FPGA_HF_ISO14443A_SNIFFER) if(negedge_cnt[3:0] == 4'b0000 && mod_type != `FPGA_HF_ISO14443A_SNIFFER)
begin begin
// Don't shift if we just loaded new data, obviously. // Don't shift if we just loaded new data, obviously.
if(negedge_cnt[6:0] != 7'd0) if(negedge_cnt[6:0] != 7'd0)
@ -487,8 +487,8 @@ reg ssp_frame;
always @(negedge adc_clk) always @(negedge adc_clk)
begin begin
if(mod_type == `FPGA_HF_ISO14443A_SNIFFER) if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
// FPGA_HF_ISO14443A_SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)): // FPGA_HF_ISO14443A_SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
begin begin
if(negedge_cnt[2:0] == 3'd0) if(negedge_cnt[2:0] == 3'd0)
ssp_clk <= 1'b1; ssp_clk <= 1'b1;
@ -508,7 +508,7 @@ begin
if(negedge_cnt[3:0] == 4'd8) if(negedge_cnt[3:0] == 4'd8)
ssp_clk <= 1'b0; ssp_clk <= 1'b0;
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame, sampled on falling edge of ssp_clk if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame, sampled on falling edge of ssp_clk
ssp_frame <= 1'b1; ssp_frame <= 1'b1;
if(negedge_cnt[6:0] == 7'd23) if(negedge_cnt[6:0] == 7'd23)
ssp_frame <= 1'b0; ssp_frame <= 1'b0;
@ -528,23 +528,23 @@ begin
if(negedge_cnt[3:0] == 4'd0) if(negedge_cnt[3:0] == 4'd0)
begin begin
// What do we communicate to the ARM // What do we communicate to the ARM
if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN) if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN)
sendbit = after_hysteresis; sendbit = after_hysteresis;
else if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD) else if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD)
/* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh? /* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
else */ else */
sendbit = fdt_indicator; sendbit = fdt_indicator;
else if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN) else if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
sendbit = curbit; sendbit = curbit;
else else
sendbit = 1'b0; sendbit = 1'b0;
end end
if(mod_type == `FPGA_HF_ISO14443A_SNIFFER) if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
// send sampled reader and tag data: // send sampled reader and tag data:
bit_to_arm = to_arm[7]; bit_to_arm = to_arm[7];
else if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD && fdt_elapsed && temp_buffer_reset) else if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
// send timing information: // send timing information:
bit_to_arm = to_arm[7]; bit_to_arm = to_arm[7];
else else

218
fpga-xc3s100e/hi_reader.v
View file

@ -19,7 +19,7 @@ module hi_reader(
output ssp_frame, ssp_din, ssp_clk; output ssp_frame, ssp_din, ssp_clk;
output dbg; output dbg;
input [1:0] subcarrier_frequency; input [1:0] subcarrier_frequency;
input [3:0] minor_mode; input [3:0] minor_mode;
assign adc_clk = ck_1356meg; // sample frequency is 13,56 MHz assign adc_clk = ck_1356meg; // sample frequency is 13,56 MHz
@ -58,7 +58,7 @@ end
reg [5:0] corr_i_cnt; reg [5:0] corr_i_cnt;
always @(negedge adc_clk) always @(negedge adc_clk)
begin begin
corr_i_cnt <= corr_i_cnt + 1; corr_i_cnt <= corr_i_cnt + 1;
end end
@ -83,28 +83,28 @@ reg [12:0] min_ci_cq_2; // min_ci_cq / 2
always @(*) always @(*)
begin begin
if (corr_i_accum[13] == 1'b0) if (corr_i_accum[13] == 1'b0)
abs_ci <= corr_i_accum; abs_ci <= corr_i_accum;
else else
abs_ci <= -corr_i_accum; abs_ci <= -corr_i_accum;
if (corr_q_accum[13] == 1'b0) if (corr_q_accum[13] == 1'b0)
abs_cq <= corr_q_accum; abs_cq <= corr_q_accum;
else else
abs_cq <= -corr_q_accum; abs_cq <= -corr_q_accum;
if (abs_ci > abs_cq) if (abs_ci > abs_cq)
begin begin
max_ci_cq <= abs_ci; max_ci_cq <= abs_ci;
min_ci_cq_2 <= abs_cq / 2; min_ci_cq_2 <= abs_cq / 2;
end end
else else
begin begin
max_ci_cq <= abs_cq; max_ci_cq <= abs_cq;
min_ci_cq_2 <= abs_ci / 2; min_ci_cq_2 <= abs_ci / 2;
end end
corr_amplitude <= max_ci_cq + min_ci_cq_2; corr_amplitude <= max_ci_cq + min_ci_cq_2;
end end
@ -115,21 +115,21 @@ reg subcarrier_Q;
always @(*) always @(*)
begin begin
if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ) if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
begin begin
subcarrier_I = ~corr_i_cnt[3]; subcarrier_I = ~corr_i_cnt[3];
subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]); subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
end end
else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ) else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
begin begin
subcarrier_I = ~corr_i_cnt[5]; subcarrier_I = ~corr_i_cnt[5];
subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]); subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
end end
else else
begin // 424 kHz begin // 424 kHz
subcarrier_I = ~corr_i_cnt[4]; subcarrier_I = ~corr_i_cnt[4];
subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]); subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
end end
end end
@ -143,64 +143,64 @@ begin
begin begin
if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE) if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE)
begin begin
// send amplitude plus 2 bits reader signal // send amplitude plus 2 bits reader signal
corr_i_out <= corr_amplitude[13:6]; corr_i_out <= corr_amplitude[13:6];
corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev}; corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
end end
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ) else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
begin begin
// Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal // Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111) if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev}; corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
else // truncate to maximum value else // truncate to maximum value
if (corr_i_accum[13] == 1'b0) if (corr_i_accum[13] == 1'b0)
corr_i_out <= {7'b0111111, after_hysteresis_prev_prev}; corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
else else
corr_i_out <= {7'b1000000, after_hysteresis_prev_prev}; corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
// Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal // Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111) if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev}; corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
else // truncate to maximum value else // truncate to maximum value
if (corr_q_accum[13] == 1'b0) if (corr_q_accum[13] == 1'b0)
corr_q_out <= {7'b0111111, after_hysteresis_prev}; corr_q_out <= {7'b0111111, after_hysteresis_prev};
else else
corr_q_out <= {7'b1000000, after_hysteresis_prev}; corr_q_out <= {7'b1000000, after_hysteresis_prev};
end end
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE) else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE)
begin begin
// send amplitude // send amplitude
corr_i_out <= {2'b00, corr_amplitude[13:8]}; corr_i_out <= {2'b00, corr_amplitude[13:8]};
corr_q_out <= corr_amplitude[7:0]; corr_q_out <= corr_amplitude[7:0];
end end
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ) else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
begin begin
// Send 8 bits of in phase tag signal // Send 8 bits of in phase tag signal
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111) if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
corr_i_out <= corr_i_accum[11:4]; corr_i_out <= corr_i_accum[11:4];
else // truncate to maximum value else // truncate to maximum value
if (corr_i_accum[13] == 1'b0) if (corr_i_accum[13] == 1'b0)
corr_i_out <= 8'b01111111; corr_i_out <= 8'b01111111;
else else
corr_i_out <= 8'b10000000; corr_i_out <= 8'b10000000;
// Send 8 bits of quadrature phase tag signal // Send 8 bits of quadrature phase tag signal
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111) if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
corr_q_out <= corr_q_accum[11:4]; corr_q_out <= corr_q_accum[11:4];
else // truncate to maximum value else // truncate to maximum value
if (corr_q_accum[13] == 1'b0) if (corr_q_accum[13] == 1'b0)
corr_q_out <= 8'b01111111; corr_q_out <= 8'b01111111;
else else
corr_q_out <= 8'b10000000; corr_q_out <= 8'b10000000;
end end
// for each Q/I pair report two reader signal samples when sniffing. Store the 1st. // for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
after_hysteresis_prev_prev <= after_hysteresis; after_hysteresis_prev_prev <= after_hysteresis;
// Initialize next correlation. // Initialize next correlation.
// Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate. // Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate.
corr_i_accum <= $signed({1'b0, adc_d}); corr_i_accum <= $signed({1'b0, adc_d});
corr_q_accum <= $signed({1'b0, adc_d}); corr_q_accum <= $signed({1'b0, adc_d});
end end
@ -217,14 +217,14 @@ begin
corr_q_accum <= corr_q_accum - $signed({1'b0, adc_d}); corr_q_accum <= corr_q_accum - $signed({1'b0, adc_d});
end end
// for each Q/I pair report two reader signal samples when sniffing. Store the 2nd. // for each Q/I pair report two reader signal samples when sniffing. Store the 2nd.
if (corr_i_cnt == 6'd32) if (corr_i_cnt == 6'd32)
after_hysteresis_prev <= after_hysteresis; after_hysteresis_prev <= after_hysteresis;
// Then the result from last time is serialized and send out to the ARM. // Then the result from last time is serialized and send out to the ARM.
// We get one report each cycle, and each report is 16 bits, so the // We get one report each cycle, and each report is 16 bits, so the
// ssp_clk should be the adc_clk divided by 64/16 = 4. // ssp_clk should be the adc_clk divided by 64/16 = 4.
// ssp_clk frequency = 13,56MHz / 4 = 3.39MHz // ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
if (corr_i_cnt[1:0] == 2'b00) if (corr_i_cnt[1:0] == 2'b00)
begin begin
@ -261,8 +261,8 @@ begin
if (corr_i_cnt[1:0] == 2'b10) if (corr_i_cnt[1:0] == 2'b10)
ssp_clk <= 1'b0; ssp_clk <= 1'b0;
// set ssp_frame signal for corr_i_cnt = 1..3 // set ssp_frame signal for corr_i_cnt = 1..3
// (send one frame with 16 Bits) // (send one frame with 16 Bits)
if (corr_i_cnt == 6'd1) if (corr_i_cnt == 6'd1)
ssp_frame <= 1'b1; ssp_frame <= 1'b1;
@ -280,11 +280,11 @@ reg [3:0] jam_counter;
always @(negedge adc_clk) always @(negedge adc_clk)
begin begin
if (corr_i_cnt == 6'd0) if (corr_i_cnt == 6'd0)
begin begin
jam_counter <= jam_counter + 1; jam_counter <= jam_counter + 1;
jam_signal <= jam_counter[1] ^ jam_counter[3]; jam_signal <= jam_counter[1] ^ jam_counter[3];
end end
end end
// Antenna drivers // Antenna drivers
@ -303,22 +303,22 @@ begin
pwr_oe4 = 1'b0; pwr_oe4 = 1'b0;
end end
else if (minor_mode == `FPGA_HF_READER_MODE_SEND_JAM) else if (minor_mode == `FPGA_HF_READER_MODE_SEND_JAM)
begin begin
pwr_hi = ck_1356meg & jam_signal; pwr_hi = ck_1356meg & jam_signal;
pwr_oe4 = 1'b0; pwr_oe4 = 1'b0;
end end
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE || minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE) || minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE)
begin // all off begin // all off
pwr_hi = 1'b0; pwr_hi = 1'b0;
pwr_oe4 = 1'b0; pwr_oe4 = 1'b0;
end end
else // receiving from tag else // receiving from tag
begin begin
pwr_hi = ck_1356meg; pwr_hi = ck_1356meg;
pwr_oe4 = 1'b0; pwr_oe4 = 1'b0;
end end
end end
// always on // always on

38
fpga-xc3s100e/hi_simulate.v
View file

@ -39,8 +39,8 @@ module hi_simulate(
// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can // Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
// always be low. // always be low.
assign pwr_hi = 1'b0; // HF antenna connected to GND assign pwr_hi = 1'b0; // HF antenna connected to GND
assign pwr_lo = 1'b0; // LF antenna connected to GND assign pwr_lo = 1'b0; // LF antenna connected to GND
// This one is all LF, so doesn't matter // This one is all LF, so doesn't matter
assign pwr_oe2 = 1'b0; assign pwr_oe2 = 1'b0;
@ -57,7 +57,7 @@ begin
if (& adc_d[7:5]) after_hysteresis <= 1'b1; // if (adc_d >= 224) if (& adc_d[7:5]) after_hysteresis <= 1'b1; // if (adc_d >= 224)
else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0; // if (adc_d <= 31) else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0; // if (adc_d <= 31)
if (adc_d >= 224) if (adc_d >= 224)
begin begin
has_been_low_for <= 12'd0; has_been_low_for <= 12'd0;
end end
@ -69,9 +69,9 @@ begin
after_hysteresis <= 1'b1; after_hysteresis <= 1'b1;
end end
else else
begin begin
has_been_low_for <= has_been_low_for + 1; has_been_low_for <= has_been_low_for + 1;
end end
end end
end end
@ -104,20 +104,20 @@ end
reg ssp_frame; reg ssp_frame;
always @(negedge adc_clk) always @(negedge adc_clk)
begin begin
if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K) if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
begin begin
if (ssp_clk_divider[8:5] == 4'd1) if (ssp_clk_divider[8:5] == 4'd1)
ssp_frame <= 1'b1; ssp_frame <= 1'b1;
if (ssp_clk_divider[8:5] == 4'd5) if (ssp_clk_divider[8:5] == 4'd5)
ssp_frame <= 1'b0; ssp_frame <= 1'b0;
end end
else else
begin begin
if (ssp_clk_divider[7:4] == 4'd1) if (ssp_clk_divider[7:4] == 4'd1)
ssp_frame <= 1'b1; ssp_frame <= 1'b1;
if (ssp_clk_divider[7:4] == 4'd5) if (ssp_clk_divider[7:4] == 4'd5)
ssp_frame <= 1'b0; ssp_frame <= 1'b0;
end end
end end
@ -147,6 +147,6 @@ always @(*)
assign pwr_oe1 = 1'b0; // 33 Ohms Load assign pwr_oe1 = 1'b0; // 33 Ohms Load
assign pwr_oe4 = modulating_carrier; // 33 Ohms Load assign pwr_oe4 = modulating_carrier; // 33 Ohms Load
// This one is always on, so that we can watch the carrier. // This one is always on, so that we can watch the carrier.
assign pwr_oe3 = 1'b0; // 10k Load assign pwr_oe3 = 1'b0; // 10k Load
endmodule endmodule