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This commit is contained in:
Philippe Teuwen 2021-09-05 00:49:57 +02:00
commit 7404695e46
9 changed files with 290 additions and 290 deletions
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52
fpga-xc3s100e/fpga_allinone.v
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@ -26,8 +26,8 @@ module fpga_hf(
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg,
output PWR_LO_EN,
input FPGA_SWITCH
output PWR_LO_EN,
input FPGA_SWITCH
);
@ -51,31 +51,31 @@ fpga_lfmod lfmod(
lfssp_frame, lfssp_din, lfssp_dout, lfssp_clk,
lfcross_hi, lfcross_lo,
lfdbg,
lfPWR_LO_EN
lfPWR_LO_EN
);
mux2_oneout mux_spck_all (FPGA_SWITCH, spck, hfspck, lfspck);
mux2_one mux_miso_all (FPGA_SWITCH, miso, hfmiso, lfmiso);
mux2_oneout mux_mosi_all (FPGA_SWITCH, mosi, hfmosi, lfmosi);
mux2_oneout mux_ncs_all (FPGA_SWITCH, ncs, hfncs, lfncs);
mux2_oneout mux_pck0_all (FPGA_SWITCH, pck0, hfpck0, lfpck0);
mux2_oneout mux_ck_1356meg_all (FPGA_SWITCH, ck_1356meg, hfck_1356meg, lfck_1356meg);
mux2_oneout mux_ck_1356megb_all (FPGA_SWITCH, ck_1356megb, hfck_1356megb, lfck_1356megb);
mux2_one mux_pwr_lo_all (FPGA_SWITCH, pwr_lo, hfpwr_lo, lfpwr_lo);
mux2_one mux_pwr_hi_all (FPGA_SWITCH, pwr_hi, hfpwr_hi, lfpwr_hi);
mux2_one mux_pwr_oe1_all (FPGA_SWITCH, pwr_oe1, hfpwr_oe1, lfpwr_oe1);
mux2_one mux_pwr_oe2_all (FPGA_SWITCH, pwr_oe2, hfpwr_oe2, lfpwr_oe2);
mux2_one mux_pwr_oe3_all (FPGA_SWITCH, pwr_oe3, hfpwr_oe3, lfpwr_oe3);
mux2_one mux_pwr_oe4_all (FPGA_SWITCH, pwr_oe4, hfpwr_oe4, lfpwr_oe4);
mux2_one mux_adc_clk_all (FPGA_SWITCH, adc_clk, hfadc_clk, lfadc_clk);
mux2_one mux_adc_noe_all (FPGA_SWITCH, adc_noe, adc_noe, lfadc_noe);
mux2_one mux_ssp_frame_all (FPGA_SWITCH, ssp_frame, hfssp_frame, lfssp_frame);
mux2_one mux_ssp_din_all (FPGA_SWITCH, ssp_din, hfssp_din, lfssp_din);
mux2_oneout mux_ssp_dout_all (FPGA_SWITCH, ssp_dout, hfssp_dout, lfssp_dout);
mux2_one mux_ssp_clk_all (FPGA_SWITCH, ssp_clk, hfssp_clk, lfssp_clk);
mux2_oneout mux_cross_hi_all (FPGA_SWITCH, cross_hi, hfcross_hi, lfcross_hi);
mux2_oneout mux_cross_lo_all (FPGA_SWITCH, cross_lo, hfcross_lo, lfcross_lo);
mux2_one mux_dbg_all (FPGA_SWITCH, dbg, hfdbg, lfdbg);
mux2_one mux_PWR_LO_EN_all (FPGA_SWITCH, PWR_LO_EN, 1'b0, lfPWR_LO_EN);
mux2_oneout mux_spck_all (FPGA_SWITCH, spck, hfspck, lfspck);
mux2_one mux_miso_all (FPGA_SWITCH, miso, hfmiso, lfmiso);
mux2_oneout mux_mosi_all (FPGA_SWITCH, mosi, hfmosi, lfmosi);
mux2_oneout mux_ncs_all (FPGA_SWITCH, ncs, hfncs, lfncs);
mux2_oneout mux_pck0_all (FPGA_SWITCH, pck0, hfpck0, lfpck0);
mux2_oneout mux_ck_1356meg_all (FPGA_SWITCH, ck_1356meg, hfck_1356meg, lfck_1356meg);
mux2_oneout mux_ck_1356megb_all (FPGA_SWITCH, ck_1356megb, hfck_1356megb, lfck_1356megb);
mux2_one mux_pwr_lo_all (FPGA_SWITCH, pwr_lo, hfpwr_lo, lfpwr_lo);
mux2_one mux_pwr_hi_all (FPGA_SWITCH, pwr_hi, hfpwr_hi, lfpwr_hi);
mux2_one mux_pwr_oe1_all (FPGA_SWITCH, pwr_oe1, hfpwr_oe1, lfpwr_oe1);
mux2_one mux_pwr_oe2_all (FPGA_SWITCH, pwr_oe2, hfpwr_oe2, lfpwr_oe2);
mux2_one mux_pwr_oe3_all (FPGA_SWITCH, pwr_oe3, hfpwr_oe3, lfpwr_oe3);
mux2_one mux_pwr_oe4_all (FPGA_SWITCH, pwr_oe4, hfpwr_oe4, lfpwr_oe4);
mux2_one mux_adc_clk_all (FPGA_SWITCH, adc_clk, hfadc_clk, lfadc_clk);
mux2_one mux_adc_noe_all (FPGA_SWITCH, adc_noe, adc_noe, lfadc_noe);
mux2_one mux_ssp_frame_all (FPGA_SWITCH, ssp_frame, hfssp_frame, lfssp_frame);
mux2_one mux_ssp_din_all (FPGA_SWITCH, ssp_din, hfssp_din, lfssp_din);
mux2_oneout mux_ssp_dout_all (FPGA_SWITCH, ssp_dout, hfssp_dout, lfssp_dout);
mux2_one mux_ssp_clk_all (FPGA_SWITCH, ssp_clk, hfssp_clk, lfssp_clk);
mux2_oneout mux_cross_hi_all (FPGA_SWITCH, cross_hi, hfcross_hi, lfcross_hi);
mux2_oneout mux_cross_lo_all (FPGA_SWITCH, cross_lo, hfcross_lo, lfcross_lo);
mux2_one mux_dbg_all (FPGA_SWITCH, dbg, hfdbg, lfdbg);
mux2_one mux_PWR_LO_EN_all (FPGA_SWITCH, PWR_LO_EN, 1'b0, lfPWR_LO_EN);
endmodule