From 6fa188062c14b5765dbf8e8aeb50d695bf076911 Mon Sep 17 00:00:00 2001 From: iceman1001 Date: Sun, 12 Jan 2020 17:30:29 +0100 Subject: [PATCH] style --- armsrc/fpgaloader.h | 6 +++--- armsrc/lfsampling.c | 12 ++++++------ client/cmdlfpac.c | 2 +- fpga/fpga_hf.v | 4 ++-- fpga/fpga_lf.v | 10 +++++----- fpga/hi_flite.v | 10 +++++----- 6 files changed, 22 insertions(+), 22 deletions(-) diff --git a/armsrc/fpgaloader.h b/armsrc/fpgaloader.h index 5399db4ed..636c5b7b7 100644 --- a/armsrc/fpgaloader.h +++ b/armsrc/fpgaloader.h @@ -25,7 +25,7 @@ Communication between ARM / FPGA is done inside armsrc/fpgaloader.c (function FpgaSendCommand) Send 16 bit command / data pair to FPGA The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - where + where C is 4bit command D is 12bit data @@ -33,7 +33,7 @@ bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -----+------------------------------------------- cmd | x x x x -major| x x x +major| x x x opt | x x divi | x x x x x x x x thres| x x x x x x x x @@ -71,7 +71,7 @@ thres| x x x x x x x x #define FPGA_MAJOR_MODE_OFF (7<<5) // D // Options for LF_READER -#define FPGA_LF_ADC_READER_FIELD 0x1 +#define FPGA_LF_ADC_READER_FIELD 0x1 // Options for LF_EDGE_DETECT #define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD FPGA_CMD_SET_USER_BYTE1 diff --git a/armsrc/lfsampling.c b/armsrc/lfsampling.c index 32865d204..3378a9f94 100644 --- a/armsrc/lfsampling.c +++ b/armsrc/lfsampling.c @@ -54,26 +54,26 @@ void printConfig() { void setSamplingConfig(sample_config *sc) { // decimation (1-8) how many bits of adc sample value to save - if (sc->decimation > 0 && sc->decimation < 8) + if (sc->decimation > 0 && sc->decimation < 8) config.decimation = sc->decimation; // bits per sample (1-8) - if (sc->bits_per_sample > 0 && sc->bits_per_sample < 8) + if (sc->bits_per_sample > 0 && sc->bits_per_sample < 8) config.bits_per_sample = sc->bits_per_sample; // if (sc->averaging > -1) config.averaging = (sc->averaging > 0) ? 1 : 0; - + // Frequency divisor (19 - 255) if (sc->divisor > 18 && sc->divisor < 256) config.divisor = sc->divisor; - + // Start saving samples when adc value larger than trigger_threshold - if (sc->trigger_threshold > -1) + if (sc->trigger_threshold > -1) config.trigger_threshold = sc->trigger_threshold; - // Skip n adc samples before saving + // Skip n adc samples before saving if (sc->samples_to_skip > -1) config.samples_to_skip = sc->samples_to_skip; diff --git a/client/cmdlfpac.c b/client/cmdlfpac.c index 63a3e16cd..24c549a4b 100644 --- a/client/cmdlfpac.c +++ b/client/cmdlfpac.c @@ -260,7 +260,7 @@ static int CmdPacSim(const char *Cmd) { rawBlocks[i] = bytes_to_num(rawBytes + (i * sizeof(uint32_t)), sizeof(uint32_t)); num_to_bytebits(rawBlocks[i], sizeof(uint32_t) * 8, bs + (i * sizeof(uint32_t) * 8)); } - + PrintAndLogEx(SUCCESS, "Simulating PAC/Stanley - ID " _YELLOW_("%s")" raw "_YELLOW_("%08X%08X%08X%08X"), cardid, rawBlocks[0], rawBlocks[1], rawBlocks[2], rawBlocks[3]); lf_nrzsim_t *payload = calloc(1, sizeof(lf_nrzsim_t) + sizeof(bs)); diff --git a/fpga/fpga_hf.v b/fpga/fpga_hf.v index 48ae7b5ec..d23b64a08 100644 --- a/fpga/fpga_hf.v +++ b/fpga/fpga_hf.v @@ -93,7 +93,7 @@ module fpga_hf( Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand() Send 16 bit command / data pair to FPGA The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - where + where C is 4bit command D is 12bit data @@ -104,7 +104,7 @@ module fpga_hf( bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -----+------------------------------------------- cmd | x x x x -major| x x x +major| x x x opt | x x divi | x x x x x x x x thres| x x x x x x x x diff --git a/fpga/fpga_lf.v b/fpga/fpga_lf.v index da681321c..dd3fe3b0b 100644 --- a/fpga/fpga_lf.v +++ b/fpga/fpga_lf.v @@ -56,7 +56,7 @@ module fpga_lf( Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand() Send 16 bit command / data pair to FPGA The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - where + where C is 4bit command D is 12bit data @@ -83,11 +83,11 @@ module fpga_lf( Each one of this major modes can have options. Currently these two major modes uses options. - FPGA_MAJOR_MODE_LF_READER - FPGA_MAJOR_MODE_LF_EDGE_DETECT - + FPGA_MAJOR_MODE_LF_READER ------------------------------------- lf_field = 1bit (FPGA_LF_ADC_READER_FIELD) - + You can send FPGA_CMD_SET_DIVISOR to set with FREQUENCY the fpga should sample at divisor = 8bits shift_reg[7:0] @@ -101,7 +101,7 @@ module fpga_lf( conf_word 12bits conf_word[7:5] = 3bit major mode. - conf_word[0] = 1bit lf_field + conf_word[0] = 1bit lf_field conf_word[1] = 1bit lf_ed_toggle_mode conf_word[7:0] = 8bit divisor conf_word[7:0] = 8bit threshold @@ -110,7 +110,7 @@ module fpga_lf( bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -----+------------------------------------------- cmd | x x x x -major| x x x +major| x x x opt | x x divi | x x x x x x x x thres| x x x x x x x x diff --git a/fpga/hi_flite.v b/fpga/hi_flite.v index aa1f12925..97d0154ea 100644 --- a/fpga/hi_flite.v +++ b/fpga/hi_flite.v @@ -1,13 +1,13 @@ /* - This code demodulates and modulates signal as described in ISO/IEC 18092. + This code demodulates and modulates signal as described in ISO/IEC 18092. That includes packets used for Felica, NFC Tag 3, etc. (which do overlap) - simple envelope following algorithm is used (modification of fail0verflow LF one) + simple envelope following algorithm is used (modification of fail0verflow LF one) is used to combat some nasty aliasing effect with testing phone (envelope looked like sine wave) Speeds supported: only 212 kbps (fc/64) for now. Todo: 414 kbps - though for reader, the selection has to come from ARM. modulation waits for market sprocket -doesn't really mean anything + though for reader, the selection has to come from ARM. modulation waits for market sprocket -doesn't really mean anything - mod_type: bits 210: + mod_type: bits 210: bit 2 : reader drive/power on/off bit 1 : speed bit, 0 : 212, 1 :424 bit 0 : listen or modulate @@ -130,7 +130,7 @@ reg ssp_din; reg prv = 1'b1; // for simple error correction in mod/demod detection, use maximum of modded/demodded in given interval. Maybe 1 bit is extra? but better safe than sorry. -reg[7:0] mid = 8'd128; +reg[7:0] mid = 8'd128; // set TAGSIM__MODULATE on ARM if we want to write... (frame would get lost if done mid-frame...) // start sending over 1s on ssp->arm when we start sending preamble