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Merge pull request #2098 from d18c7db/master

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Fix BUGBUG in fpgaloader.h and some other small cleanups
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Iceman 2023-08-29 16:43:23 +02:00 • committed by GitHub
commit 6059bff05d
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6 changed files with 261 additions and 218 deletions
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3
armsrc/fpgaloader.c
View file

@ -162,8 +162,7 @@ void FpgaSetupSsc(uint16_t fpga_mode) {
// 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync // 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync
// pulse, no output sync // pulse, no output sync
if (((fpga_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_READER || if (((fpga_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_READER ) &&
(fpga_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_FSK_READER) &&
(FpgaGetCurrent() == FPGA_BITSTREAM_HF || FpgaGetCurrent() == FPGA_BITSTREAM_HF_15)) { (FpgaGetCurrent() == FPGA_BITSTREAM_HF || FpgaGetCurrent() == FPGA_BITSTREAM_HF_15)) {
AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0); AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
} else { } else {

180
armsrc/fpgaloader.h
View file

@ -1,5 +1,4 @@
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// Copyright (C) Jonathan Westhues, April 2006
// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details. // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
// //
// This program is free software: you can redistribute it and/or modify // This program is free software: you can redistribute it and/or modify
@ -32,80 +31,116 @@
#define FPGA_BITSTREAM_HF_15 4 #define FPGA_BITSTREAM_HF_15 4
/* /*
Communication between ARM / FPGA is done inside armsrc/fpgaloader.c (function FpgaSendCommand) Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
Send 16 bit command / data pair to FPGA Send 16 bit command / data pair to FPGA with the bit format:
BUGBUG -- Conflicts with information in ../fpga/define.v +------ frame layout circa 2020 ------------------+
| 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
+-------------------------------------------------+
| C C C C M M M M P P P P P P P P | C = FPGA_CMD_SET_CONFREG, M = FPGA_MAJOR_MODE_*, P = FPGA_LF_* or FPGA_HF_* parameter
| C C C C D D D D D D D D | C = FPGA_CMD_SET_DIVISOR, D = divisor
| C C C C T T T T T T T T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, T = threshold
| C C C C E | C = FPGA_CMD_TRACE_ENABLE, E=0 off, E=1 on
+-------------------------------------------------+
The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 +------ frame layout current ---------------------+
where | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
C is 4bit command +-------------------------------------------------+
D is 12bit data | C C C C M M M P P P P P P | C = FPGA_CMD_SET_CONFREG, M = FPGA_MAJOR_MODE_*, P = FPGA_LF_* or FPGA_HF_* parameter
| C C C C D D D D D D D D | C = FPGA_CMD_SET_DIVISOR, D = divisor
| C C C C T T T T T T T T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, T = threshold
| C C C C E | C = FPGA_CMD_TRACE_ENABLE, E=0 off, E=1 on
+-------------------------------------------------+
shift_reg receive this 16bit frame
LF command
----------
shift_reg[15:12] == 4bit command
LF has three commands (FPGA_CMD_SET_CONFREG, FPGA_CMD_SET_DIVISOR, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD)
Current commands uses only 2bits. We have room for up to 4bits of commands total (7).
LF data
-------
shift_reg[11:0] == 12bit data
lf data is divided into MAJOR MODES and configuration values.
The major modes uses 3bits (0,1,2,3,7 | 000, 001, 010, 011, 111)
000 FPGA_MAJOR_MODE_LF_READER = Act as LF reader (modulate)
001 FPGA_MAJOR_MODE_LF_EDGE_DETECT = Simulate LF
010 FPGA_MAJOR_MODE_LF_PASSTHRU = Passthrough mode, CROSS_LO line connected to SSP_DIN. SSP_DOUT logic level controls if we modulate / listening
011 FPGA_MAJOR_MODE_LF_ADC = refactor hitag2, clear ADC sampling
111 FPGA_MAJOR_MODE_OFF = turn off sampling.
Each one of this major modes can have options. Currently these two major modes uses options.
- FPGA_MAJOR_MODE_LF_READER
- FPGA_MAJOR_MODE_LF_EDGE_DETECT
FPGA_MAJOR_MODE_LF_READER
-------------------------------------
lf_field = 1bit (FPGA_LF_ADC_READER_FIELD)
You can send FPGA_CMD_SET_DIVISOR to set with FREQUENCY the fpga should sample at
divisor = 8bits shift_reg[7:0]
FPGA_MAJOR_MODE_LF_EDGE_DETECT
------------------------------------------
lf_ed_toggle_mode = 1bits
lf_ed_threshold = 8bits threshold defaults to 127
You can send FPGA_CMD_SET_EDGE_DETECT_THRESHOLD to set a custom threshold
lf_ed_threshold = 8bits threshold value.
conf_word 12bits
conf_word[7:5] = 3bit major mode.
conf_word[0] = 1bit lf_field
conf_word[1] = 1bit lf_ed_toggle_mode
conf_word[7:0] = 8bit divisor
conf_word[7:0] = 8bit threshold
-----+--------- frame layout --------------------
bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-----+-------------------------------------------
cmd | x x x x
major| x x x
opt | x x
divi | x x x x x x x x
thres| x x x x x x x x
-----+-------------------------------------------
*/ */
// Defining commands, modes and options. This must be aligned to the definitions in fpga/define.v
// Definitions for the FPGA commands.
// BOTH HF / LF
#define FPGA_CMD_SET_CONFREG (1<<12) // C
// LF
#define FPGA_CMD_SET_DIVISOR (2<<12) // C
#define FPGA_CMD_SET_USER_BYTE1 (3<<12) // C
// HF
#define FPGA_CMD_TRACE_ENABLE (2<<12) // C
// Definitions for the FPGA configuration word.
#define FPGA_MAJOR_MODE_MASK 0x01C0 #define FPGA_MAJOR_MODE_MASK 0x01C0
#define FPGA_MINOR_MODE_MASK 0x003F #define FPGA_MINOR_MODE_MASK 0x003F
// LF // Definitions for the FPGA commands.
#define FPGA_CMD_SET_CONFREG (1<<12)
#define FPGA_CMD_SET_DIVISOR (2<<12)
#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD (3<<12)
#define FPGA_CMD_TRACE_ENABLE (2<<12)
// Major modes
#define FPGA_MAJOR_MODE_LF_READER (0<<6) #define FPGA_MAJOR_MODE_LF_READER (0<<6)
#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<6) #define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<6)
#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<6) #define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<6)
#define FPGA_MAJOR_MODE_LF_ADC (3<<6) #define FPGA_MAJOR_MODE_LF_ADC (3<<6)
// HF #define FPGA_MAJOR_MODE_HF_READER (0<<6)
#define FPGA_MAJOR_MODE_HF_READER (0<<6) // D #define FPGA_MAJOR_MODE_HF_SIMULATOR (1<<6)
#define FPGA_MAJOR_MODE_HF_SIMULATOR (1<<6) // D #define FPGA_MAJOR_MODE_HF_ISO14443A (2<<6)
#define FPGA_MAJOR_MODE_HF_ISO14443A (2<<6) // D #define FPGA_MAJOR_MODE_HF_SNIFF (3<<6)
#define FPGA_MAJOR_MODE_HF_SNIFF (3<<6) // D #define FPGA_MAJOR_MODE_HF_ISO18092 (4<<6)
#define FPGA_MAJOR_MODE_HF_ISO18092 (4<<6) // D #define FPGA_MAJOR_MODE_HF_GET_TRACE (5<<6)
#define FPGA_MAJOR_MODE_HF_GET_TRACE (5<<6) // D #define FPGA_MAJOR_MODE_OFF (7<<6)
#define FPGA_MAJOR_MODE_HF_FSK_READER (6<<6) // D
// BOTH HF / LF
#define FPGA_MAJOR_MODE_OFF (7<<6) // D
// Options for LF_READER // Options for LF_READER
#define FPGA_LF_ADC_READER_FIELD 0x1 #define FPGA_LF_ADC_READER_FIELD ( 1 )
// Options for LF_EDGE_DETECT // Options for LF_EDGE_DETECT
#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD FPGA_CMD_SET_USER_BYTE1 #define FPGA_LF_EDGE_DETECT_READER_FIELD ( 1 )
#define FPGA_LF_EDGE_DETECT_READER_FIELD 0x1 #define FPGA_LF_EDGE_DETECT_TOGGLE_MODE ( 2 )
#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 0x2
// Options for the HF reader // Options for the generic HF reader
#define FPGA_HF_READER_MODE_RECEIVE_IQ (0<<0) #define FPGA_HF_READER_MODE_RECEIVE_IQ ( 0 )
#define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE (1<<0) #define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE ( 1 )
#define FPGA_HF_READER_MODE_RECEIVE_PHASE (2<<0) #define FPGA_HF_READER_MODE_RECEIVE_PHASE ( 2 )
#define FPGA_HF_READER_MODE_SEND_FULL_MOD (3<<0) #define FPGA_HF_READER_MODE_SEND_FULL_MOD ( 3 )
#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD (4<<0) #define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD ( 4 )
#define FPGA_HF_READER_MODE_SNIFF_IQ (5<<0) #define FPGA_HF_READER_MODE_SNIFF_IQ ( 5 )
#define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE (6<<0) #define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE ( 6 )
#define FPGA_HF_READER_MODE_SNIFF_PHASE (7<<0) #define FPGA_HF_READER_MODE_SNIFF_PHASE ( 7 )
#define FPGA_HF_READER_MODE_SEND_JAM (8<<0) #define FPGA_HF_READER_MODE_SEND_JAM ( 8 )
#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4 (9<<0) #define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4 ( 9 )
#define FPGA_HF_READER_SUBCARRIER_848_KHZ (0<<4) #define FPGA_HF_READER_SUBCARRIER_848_KHZ (0<<4)
#define FPGA_HF_READER_SUBCARRIER_424_KHZ (1<<4) #define FPGA_HF_READER_SUBCARRIER_424_KHZ (1<<4)
@ -113,24 +148,23 @@ thres| x x x x x x x x
#define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ (3<<4) #define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ (3<<4)
// Options for the HF simulated tag, how to modulate // Options for the HF simulated tag, how to modulate
#define FPGA_HF_SIMULATOR_NO_MODULATION 0x0 // 0000 #define FPGA_HF_SIMULATOR_NO_MODULATION ( 0 )
#define FPGA_HF_SIMULATOR_MODULATE_BPSK 0x1 // 0001 #define FPGA_HF_SIMULATOR_MODULATE_BPSK ( 1 )
#define FPGA_HF_SIMULATOR_MODULATE_212K 0x2 // 0010 #define FPGA_HF_SIMULATOR_MODULATE_212K ( 2 )
#define FPGA_HF_SIMULATOR_MODULATE_424K 0x4 // 0100 #define FPGA_HF_SIMULATOR_MODULATE_424K ( 4 )
#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5 // 0101 #define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT ( 5 )
// no 848K
// Options for ISO14443A // Options for ISO14443A
#define FPGA_HF_ISO14443A_SNIFFER 0x0 #define FPGA_HF_ISO14443A_SNIFFER ( 0 )
#define FPGA_HF_ISO14443A_TAGSIM_LISTEN 0x1 #define FPGA_HF_ISO14443A_TAGSIM_LISTEN ( 1 )
#define FPGA_HF_ISO14443A_TAGSIM_MOD 0x2 #define FPGA_HF_ISO14443A_TAGSIM_MOD ( 2 )
#define FPGA_HF_ISO14443A_READER_LISTEN 0x3 #define FPGA_HF_ISO14443A_READER_LISTEN ( 3 )
#define FPGA_HF_ISO14443A_READER_MOD 0x4 #define FPGA_HF_ISO14443A_READER_MOD ( 4 )
//options for Felica. // Options for ISO18092 / Felica
#define FPGA_HF_ISO18092_FLAG_NOMOD 0x1 // 0001 disable modulation module #define FPGA_HF_ISO18092_FLAG_NOMOD ( 1 ) // 0001 disable modulation module
#define FPGA_HF_ISO18092_FLAG_424K 0x2 // 0010 should enable 414k mode (untested). No autodetect #define FPGA_HF_ISO18092_FLAG_424K ( 2 ) // 0010 should enable 414k mode (untested). No autodetect
#define FPGA_HF_ISO18092_FLAG_READER 0x4 // 0100 enables antenna power, to act as a reader instead of tag #define FPGA_HF_ISO18092_FLAG_READER ( 4 ) // 0100 enables antenna power, to act as a reader instead of tag
void FpgaSendCommand(uint16_t cmd, uint16_t v); void FpgaSendCommand(uint16_t cmd, uint16_t v);
void FpgaWriteConfWord(uint16_t v); void FpgaWriteConfWord(uint16_t v);

2
doc/clocks.md
View file

@ -49,7 +49,7 @@ Basic units of time you will run into in the RFID world.
125 kHz = 1/ 125 000 = 8 micro seconds 125 kHz = 1/ 125 000 = 8 micro seconds
``` ```
Given these units the following clocks used by Proxmark3 wil make more sense. Given these units the following clocks used by Proxmark3 will make more sense.
Like the SSP Clock running at 3.39 MHz. Like the SSP Clock running at 3.39 MHz.
3.39 MHz = 1 / 3 390 000 = 294,98 nano seconds = 0,2949 micro seconds 3.39 MHz = 1 / 3 390 000 = 294,98 nano seconds = 0,2949 micro seconds

3
fpga/hi_sniffer.v
View file

@ -48,9 +48,6 @@ assign ssp_din = adc_d_out[0];
always @(posedge ssp_clk) always @(posedge ssp_clk)
begin begin
if(ssp_cnt[2:0] == 3'd7)
ssp_cnt[2:0] <= 3'd0;
else
ssp_cnt <= ssp_cnt + 1; ssp_cnt <= ssp_cnt + 1;
if(ssp_cnt[2:0] == 3'b000) // set frame length if(ssp_cnt[2:0] == 3'b000) // set frame length

5
fpga/lo_read.v
View file

@ -54,10 +54,7 @@ begin
if ((pck_cnt == 8'd7) && !pck_divclk) if ((pck_cnt == 8'd7) && !pck_divclk)
to_arm_shiftreg <= adc_d; to_arm_shiftreg <= adc_d;
else else
begin to_arm_shiftreg <= {to_arm_shiftreg[6:0], 1'b0};
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
to_arm_shiftreg[0] <= 1'b0;
end
end end
// ADC samples on falling edge of adc_clk, data available on the rising edge // ADC samples on falling edge of adc_clk, data available on the rising edge

32
include/at91sam7s512.h
View file

@ -1,7 +1,7 @@
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET - // ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation // Copyright (c) 2008, Atmel Corporation
// //
// All rights reserved. // All rights reserved.
// //
@ -27,14 +27,14 @@
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// File Name : AT91SAM7S512.h // File Name : AT91SAM7S512.h
// Object : AT91SAM7S512 definitions // Object : AT91SAM7S512 definitions
// Generated : AT91 SW Application Group 07/07/2008 (16:13:20) // Generated : AT91 SW Application Group 01/23/2009 (11:51:35)
// //
// CVS Reference : /AT91SAM7S512.pl/1.6/Wed Aug 30 14:08:44 2006// // CVS Reference : /AT91SAM7S512.pl/1.6/Wed Jan 21 10:52:45 2009//
// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// // CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005//
// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// // CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006//
// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// // CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005//
// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// // CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// // CVS Reference : /UDP_4ept.pl/1.1/Wed Jan 21 10:53:24 2009//
// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// // CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// // CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// // CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
@ -48,7 +48,7 @@
// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// // CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// // CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// // CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// // CVS Reference : /TC_6082A.pl/1.8/Fri Oct 17 13:27:58 2008//
// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// // CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005// // CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005//
// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005// // CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005//
@ -337,7 +337,7 @@ typedef struct _AT91S_DBGU {
#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register #define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register #define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register #define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
//#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register #define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register #define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register #define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
@ -1455,12 +1455,12 @@ typedef struct _AT91S_TC {
#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE (0x1 << 15) // (TC) #define AT91C_TC_WAVE (0x1 << 15) // (TC)
#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
#define T91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear #define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle #define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection #define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
#define T91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None #define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA #define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
@ -1533,10 +1533,21 @@ typedef struct _AT91S_TCB {
AT91_REG Reserved2[4]; // AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register AT91_REG TCB_BMR; // TC Block Mode Register
AT91_REG Reserved3[9]; //
AT91_REG TCB_ADDRSIZE; // TC ADDRSIZE REGISTER
AT91_REG TCB_IPNAME1; // TC IPNAME1 REGISTER
AT91_REG TCB_IPNAME2; // TC IPNAME2 REGISTER
AT91_REG TCB_FEATURES; // TC FEATURES REGISTER
AT91_REG TCB_VER; // Version Register
} AT91S_TCB, *AT91PS_TCB; } AT91S_TCB, *AT91PS_TCB;
#else #else
#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register #define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register #define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
#define TC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (TC_ADDRSIZE) TC ADDRSIZE REGISTER
#define TC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (TC_IPNAME1) TC IPNAME1 REGISTER
#define TC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (TC_IPNAME2) TC IPNAME2 REGISTER
#define TC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (TC_FEATURES) TC FEATURES REGISTER
#define TC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (TC_VER) Version Register
#endif #endif
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
@ -2048,8 +2059,13 @@ typedef struct _AT91S_UDP {
#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register #define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register #define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
// ========== Register definition for TCB peripheral ========== // ========== Register definition for TCB peripheral ==========
#define AT91C_TCB_ADDRSIZE (AT91_CAST(AT91_REG *) 0xFFFA00EC) // (TCB) TC ADDRSIZE REGISTER
#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register #define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
#define AT91C_TCB_VER (AT91_CAST(AT91_REG *) 0xFFFA00FC) // (TCB) Version Register
#define AT91C_TCB_FEATURES (AT91_CAST(AT91_REG *) 0xFFFA00F8) // (TCB) TC FEATURES REGISTER
#define AT91C_TCB_IPNAME1 (AT91_CAST(AT91_REG *) 0xFFFA00F0) // (TCB) TC IPNAME1 REGISTER
#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register #define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
#define AT91C_TCB_IPNAME2 (AT91_CAST(AT91_REG *) 0xFFFA00F4) // (TCB) TC IPNAME2 REGISTER
// ========== Register definition for PWMC_CH3 peripheral ========== // ========== Register definition for PWMC_CH3 peripheral ==========
#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register #define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved #define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved