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iceman1001
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442bab0706
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1 changed files with 129 additions and 175 deletions
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@ -1,11 +1,17 @@
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/*
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This code demodulates and modulates signal as described in ISO/IEC 18092.
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That includes packets used for Felica, NFC Tag 3, etc. (which do overlap)
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simple envelope following algorithm is used (modification of fail0verflow LF one)
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is used to combat some nasty aliasing effect with testing phone (envelope looked like sine wave)
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//this code demodulates and modulates signal as described in ISO/IEC 18092. That includes packets used for Felica, NFC Tag 3, etc. (which do overlap)
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//simple envelope following algorithm is used (modification of fail0verflow LF one) is used to combat some nasty aliasing effect with testing phone (envelope looked like sine wave)
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// only 212 kbps (fc/64) for now 414 is relatively straightforward... though for reader, the selection has to come from ARM
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// modulation waits for
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//market sprocket -doesn't really mean anything ;)
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//redefining mod_type: bits 210: bit 2 - reader drive/power on/off, bit 1 - speed bit, 0:212, 1 -424 bit 0: listen or modulate
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Speeds supported: only 212 kbps (fc/64) for now. Todo: 414 kbps
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though for reader, the selection has to come from ARM. modulation waits for market sprocket -doesn't really mean anything
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mod_type: bits 210:
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bit 2 : reader drive/power on/off
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bit 1 : speed bit, 0 : 212, 1 :424
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bit 0 : listen or modulate
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*/
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module hi_flite(
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pck0, ck_1356meg, ck_1356megb,
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@ -14,7 +20,7 @@ module hi_flite(
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg,
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mod_type // used
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mod_type
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);
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input pck0, ck_1356meg, ck_1356megb;
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@ -25,7 +31,7 @@ module hi_flite(
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input [2:0] mod_type; // used.
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input [2:0] mod_type;
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assign dbg=0;
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wire power = mod_type[2];
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@ -34,17 +40,12 @@ wire disabl= mod_type[0];
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// Most off, oe4 for modulation;
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// Trying reader emulation (would presumably just require switching power on, but I am not sure)
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//;// 1'b0;
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assign pwr_lo = 1'b0;
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// 512x64/fc -wait before ts0, 32768 ticks
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// tslot: 256*64/fc
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assign adc_clk = ck_1356meg;
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///heuristic values for initial thresholds. seem to work OK
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`define imin 70 // (13'd256)
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`define imax 180 // (-13'd256)
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@ -54,27 +55,22 @@ assign adc_clk = ck_1356meg;
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`define min_bitdelay_212 8
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//minimum values and corresponding thresholds
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reg [8:0] curmin=`imin;
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reg [8:0] curminthres=`ithrmin;
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reg [8:0] curmaxthres=`ithrmax;
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reg [8:0] curmax=`imax;
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//signal state, 1-not modulated, 0 -modulated
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reg after_hysteresis = 1'b1;
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//state machine for envelope tracking
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reg [1:0] state=1'd0;
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//lower edge detected, trying to detect first bit of SYNC (b24d, 1011001001001101)
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reg try_sync=1'b0;
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//detected first sync bit, phase frozen
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reg did_sync=0;
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`define bithalf_212 32 // half-bit length for 212 kbit
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`define bitmlen_212 63 // bit transition edge
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@ -111,17 +107,7 @@ begin
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if( ((~speed) && (ssp_cnt[5:0] == 6'b000000)) || (speed && (ssp_cnt[4:0] == 5'b00000)))
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begin
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ssp_clk <= 1'b1;
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// if(mod_type[2])
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// begin
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// ssp_din<=outp[0];//after_hysteresis;
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//outp<={1'b0,outp[7:1]};
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// end
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// else
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ssp_din <= curbit;
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//sample ssp_dout
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end
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if( ( (~speed) && (ssp_cnt[5:0] == 6'b100000)) ||(speed && ssp_cnt[4:0] == 5'b10000))
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ssp_clk <= 1'b0;
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@ -137,46 +123,27 @@ begin
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end
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end
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//send current bit (detected in SNIFF mode or the one being modulated in MOD mode, 0 otherwise)
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reg ssp_din;//= outp[0];
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reg ssp_din;
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//previous signal value, mostly to detect SYNC
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reg prv = 1'b1;
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reg[7:0] mid=8'd128; //for simple error correction in mod/demod detection, use maximum of modded/demodded in given interval. Maybe 1 bit is extra? but better safe than sorry.
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// for simple error correction in mod/demod detection, use maximum of modded/demodded in given interval. Maybe 1 bit is extra? but better safe than sorry.
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reg[7:0] mid = 8'd128;
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// set TAGSIM__MODULATE on ARM if we want to write... (frame would get lost if done mid-frame...)
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// start sending over 1s on ssp->arm when we start sending preamble
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reg counting_desync=1'b0; // are we counting bits since last frame?
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reg sending=1'b0; // are we actively modulating?
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reg [11:0] bit_counts=12'd0;///for timeslots... only support ts=0 for now, at 212 speed -512 fullbits from end of frame. One hopes. might remove those?
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// reg sending = 1'b0; // are we actively modulating?
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reg [11:0] bit_counts = 12'd0; // for timeslots. only support ts=0 for now, at 212 speed -512 fullbits from end of frame. One hopes. might remove those?
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//reg [2:0]old_mod;
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//always @(mod_type) //when moving from modulate_mode
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//begin
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//if (mod_type[2]==1&&old_mod[2]==0)
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// bit_counts=0;
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//old_mod=mod_type;
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//end
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//we need some way to flush bit_counts triggers on mod_type changes don't compile
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reg dlay;
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always @(negedge adc_clk) // every data ping?
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begin
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//envelope follow code...
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////////////
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//move the counter to the outside...
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// if (adc_d>=curminthres||try_sync)
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if (fccount == bitmlen)
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begin
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if ((~try_sync) && (adc_d < curminthres) && disabl )
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@ -187,20 +154,16 @@ begin
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begin
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fccount <= 0;
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end
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// if (counting_desync)
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// begin
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dlay <= ssp_dout;
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if (bit_counts > 768) // should be over ts0 now, without ARM interference... stop counting...
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begin
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bit_counts <= 0;
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// counting_desync<=0;
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end
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else
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if((power))
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if (power)
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bit_counts <= 0;
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else
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bit_counts <= bit_counts + 1;
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// end
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end
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else
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begin
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@ -214,7 +177,8 @@ begin
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end
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end
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if (adc_d>curmaxthres) //rising edge
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// rising edge
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if (adc_d > curmaxthres)
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begin
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case (state)
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0: begin
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@ -264,7 +228,6 @@ begin
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if (~try_sync ) //begin modulation, lower edge...
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begin
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try_sync <= 1;
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//counting_desync<=1'b0;
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fccount <= 1;
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did_sync <= 0;
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curbit <= 0;
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@ -288,7 +251,6 @@ begin
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if (tsinceedge >= (128))
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begin
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//we might need to start counting... assuming ARM wants to reply to the frame.
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// counting_desync<=1'b1;
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bit_counts <= 1;// i think? 128 is about 2 bits passed... but 1 also works
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try_sync <= 0;
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did_sync <= 0;//desync
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@ -308,8 +270,6 @@ begin
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end
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if (try_sync && tsinceedge < 128)
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begin
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//detect bits in their middle ssp sampling is in sync, so it would sample all bits in order
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@ -376,7 +336,7 @@ begin
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else
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begin
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end
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sending <=0;
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// sending <= 0;
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end
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//put modulation here to maintain the correct clock. Seems that some readers are sensitive to that
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reg pwr_hi;
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@ -406,11 +366,5 @@ else
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pwr_oe4 <= mod;
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end
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end
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//assign pwr_oe4 = 1'b0;// mod_sig_coil & (modulate_mode)&sending & (~mod_type[2]);
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//try shallow mod for reader?
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//assign pwr_hi= (mod_type[2]) & ck_1356megb;
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//assign pwr_oe1= 1'b0; //mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
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//assign pwr_oe2 = 1'b0;// mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
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//assign pwr_oe3 = 1'b0; //mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
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endmodule
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