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make install: half way

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This commit is contained in:
Philippe Teuwen 2019-08-30 21:55:13 +02:00
commit 4fdb5a2f4b
10 changed files with 112 additions and 58 deletions
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16
fpga/Makefile
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@ -1,36 +1,36 @@
all: fpga_lf.bit fpga_hf.bit
clean:
$(Q)$(DELETE) *.bgn *.drc *.ncd *.ngd *_par.xrpt *-placed.* *-placed_pad.* *_usage.xml xst_hf.srp xst_lf.srp
$(Q)$(DELETE) *.map *.ngc *.xrpt *.pcf *.rbt *_auto_* *.bld *.mrp *.ngm *.unroutes *_summary.xml netlist.lst xst
$(Q)$(RM) *.bgn *.drc *.ncd *.ngd *_par.xrpt *-placed.* *-placed_pad.* *_usage.xml xst_hf.srp xst_lf.srp
$(Q)$(RM) *.map *.ngc *.xrpt *.pcf *.rbt *_auto_* *.bld *.mrp *.ngm *.unroutes *_summary.xml netlist.lst xst
fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_read_tx.v hi_read_rx_xcorr.v hi_iso14443a.v hi_sniffer.v hi_flite.v
$(Q)$(DELETE) $@
$(Q)$(RM) $@
$(info [-] XST $@)
$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_hf.scr
fpga_lf.ngc: fpga_lf.v fpga.ucf xst_lf.scr util.v clk_divider.v lo_edge_detect.v lo_read.v lo_passthru.v lp20khz_1MSa_iir_filter.v min_max_tracker.v lf_edge_detect.v
$(Q)$(DELETE) $@
$(Q)$(RM) $@
$(info [-] XST $@)
$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_lf.scr
%.ngd: %.ngc
$(Q)$(DELETE) $@
$(Q)$(RM) $@
$(info [-] NGD $@)
$(Q)$(XILINX_TOOLS_PREFIX)ngdbuild -aul -p xc2s30-5-vq100 -nt timestamp -uc fpga.ucf $< $@
%.ncd: %.ngd
$(Q)$(DELETE) $@
$(Q)$(RM) $@
$(info [-] MAP $@)
$(Q)$(XILINX_TOOLS_PREFIX)map -p xc2s30-5-vq100 $<
%-placed.ncd: %.ncd
$(Q)$(DELETE) $@
$(Q)$(RM) $@
$(info [-] PAR $@)
$(Q)$(XILINX_TOOLS_PREFIX)par $< $@
%.bit: %-placed.ncd
$(Q)$(DELETE) $@ $*.drc $*.rbt
$(Q)$(RM) $@ $*.drc $*.rbt
$(info [=] BITGEN $@)
$(Q)$(XILINX_TOOLS_PREFIX)bitgen $< $@