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get rid of tabs
This commit is contained in:
Philippe Teuwen
parent
d0889cb70f
commit
491adacb94
18 changed files with 998 additions and 998 deletions
218
fpga/hi_reader.v
218
fpga/hi_reader.v
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@ -19,7 +19,7 @@ module hi_reader(
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output ssp_frame, ssp_din, ssp_clk;
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output dbg;
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input [1:0] subcarrier_frequency;
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input [3:0] minor_mode;
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input [3:0] minor_mode;
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assign adc_clk = ck_1356meg; // sample frequency is 13,56 MHz
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@ -58,7 +58,7 @@ end
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reg [5:0] corr_i_cnt;
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always @(negedge adc_clk)
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begin
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corr_i_cnt <= corr_i_cnt + 1;
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corr_i_cnt <= corr_i_cnt + 1;
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end
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@ -83,28 +83,28 @@ reg [12:0] min_ci_cq_2; // min_ci_cq / 2
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always @(*)
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begin
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if (corr_i_accum[13] == 1'b0)
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abs_ci <= corr_i_accum;
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else
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abs_ci <= -corr_i_accum;
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if (corr_i_accum[13] == 1'b0)
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abs_ci <= corr_i_accum;
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else
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abs_ci <= -corr_i_accum;
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if (corr_q_accum[13] == 1'b0)
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abs_cq <= corr_q_accum;
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else
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abs_cq <= -corr_q_accum;
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if (corr_q_accum[13] == 1'b0)
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abs_cq <= corr_q_accum;
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else
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abs_cq <= -corr_q_accum;
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if (abs_ci > abs_cq)
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begin
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max_ci_cq <= abs_ci;
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min_ci_cq_2 <= abs_cq / 2;
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end
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else
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begin
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max_ci_cq <= abs_cq;
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min_ci_cq_2 <= abs_ci / 2;
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end
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if (abs_ci > abs_cq)
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begin
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max_ci_cq <= abs_ci;
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min_ci_cq_2 <= abs_cq / 2;
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end
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else
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begin
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max_ci_cq <= abs_cq;
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min_ci_cq_2 <= abs_ci / 2;
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end
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corr_amplitude <= max_ci_cq + min_ci_cq_2;
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corr_amplitude <= max_ci_cq + min_ci_cq_2;
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end
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@ -115,21 +115,21 @@ reg subcarrier_Q;
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always @(*)
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begin
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if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
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begin
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subcarrier_I = ~corr_i_cnt[3];
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subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
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end
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else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
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begin
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subcarrier_I = ~corr_i_cnt[5];
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subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
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end
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else
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begin // 424 kHz
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subcarrier_I = ~corr_i_cnt[4];
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subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
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end
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if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
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begin
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subcarrier_I = ~corr_i_cnt[3];
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subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
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end
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else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
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begin
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subcarrier_I = ~corr_i_cnt[5];
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subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
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end
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else
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begin // 424 kHz
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subcarrier_I = ~corr_i_cnt[4];
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subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
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end
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end
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@ -143,64 +143,64 @@ begin
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begin
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if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE)
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begin
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// send amplitude plus 2 bits reader signal
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corr_i_out <= corr_amplitude[13:6];
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corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
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begin
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// send amplitude plus 2 bits reader signal
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corr_i_out <= corr_amplitude[13:6];
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corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
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begin
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// Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
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if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
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corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
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else // truncate to maximum value
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if (corr_i_accum[13] == 1'b0)
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corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
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else
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corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
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// Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
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if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
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corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
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else // truncate to maximum value
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if (corr_i_accum[13] == 1'b0)
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corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
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else
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corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
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// Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
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if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
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corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
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else // truncate to maximum value
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if (corr_q_accum[13] == 1'b0)
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corr_q_out <= {7'b0111111, after_hysteresis_prev};
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else
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corr_q_out <= {7'b1000000, after_hysteresis_prev};
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end
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// Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
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if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
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corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
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else // truncate to maximum value
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if (corr_q_accum[13] == 1'b0)
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corr_q_out <= {7'b0111111, after_hysteresis_prev};
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else
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corr_q_out <= {7'b1000000, after_hysteresis_prev};
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE)
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begin
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// send amplitude
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corr_i_out <= {2'b00, corr_amplitude[13:8]};
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corr_q_out <= corr_amplitude[7:0];
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
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begin
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// send amplitude
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corr_i_out <= {2'b00, corr_amplitude[13:8]};
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corr_q_out <= corr_amplitude[7:0];
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
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begin
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// Send 8 bits of in phase tag signal
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if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
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corr_i_out <= corr_i_accum[11:4];
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else // truncate to maximum value
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if (corr_i_accum[13] == 1'b0)
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corr_i_out <= 8'b01111111;
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else
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corr_i_out <= 8'b10000000;
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// Send 8 bits of in phase tag signal
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if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
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corr_i_out <= corr_i_accum[11:4];
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else // truncate to maximum value
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if (corr_i_accum[13] == 1'b0)
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corr_i_out <= 8'b01111111;
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else
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corr_i_out <= 8'b10000000;
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// Send 8 bits of quadrature phase tag signal
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if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
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corr_q_out <= corr_q_accum[11:4];
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else // truncate to maximum value
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if (corr_q_accum[13] == 1'b0)
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corr_q_out <= 8'b01111111;
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else
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corr_q_out <= 8'b10000000;
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end
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// Send 8 bits of quadrature phase tag signal
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if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
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corr_q_out <= corr_q_accum[11:4];
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else // truncate to maximum value
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if (corr_q_accum[13] == 1'b0)
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corr_q_out <= 8'b01111111;
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else
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corr_q_out <= 8'b10000000;
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end
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// for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
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after_hysteresis_prev_prev <= after_hysteresis;
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// for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
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after_hysteresis_prev_prev <= after_hysteresis;
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// Initialize next correlation.
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// Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate.
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// Initialize next correlation.
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// Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate.
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corr_i_accum <= $signed({1'b0, adc_d});
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corr_q_accum <= $signed({1'b0, adc_d});
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end
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@ -217,14 +217,14 @@ begin
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corr_q_accum <= corr_q_accum - $signed({1'b0, adc_d});
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end
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// for each Q/I pair report two reader signal samples when sniffing. Store the 2nd.
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// for each Q/I pair report two reader signal samples when sniffing. Store the 2nd.
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if (corr_i_cnt == 6'd32)
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after_hysteresis_prev <= after_hysteresis;
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// Then the result from last time is serialized and send out to the ARM.
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// We get one report each cycle, and each report is 16 bits, so the
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// ssp_clk should be the adc_clk divided by 64/16 = 4.
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// ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
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// ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
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if (corr_i_cnt[1:0] == 2'b00)
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begin
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@ -261,8 +261,8 @@ begin
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if (corr_i_cnt[1:0] == 2'b10)
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ssp_clk <= 1'b0;
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// set ssp_frame signal for corr_i_cnt = 1..3
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// (send one frame with 16 Bits)
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// set ssp_frame signal for corr_i_cnt = 1..3
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// (send one frame with 16 Bits)
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if (corr_i_cnt == 6'd1)
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ssp_frame <= 1'b1;
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@ -280,11 +280,11 @@ reg [3:0] jam_counter;
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always @(negedge adc_clk)
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begin
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if (corr_i_cnt == 6'd0)
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begin
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jam_counter <= jam_counter + 1;
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jam_signal <= jam_counter[1] ^ jam_counter[3];
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end
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if (corr_i_cnt == 6'd0)
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begin
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jam_counter <= jam_counter + 1;
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jam_signal <= jam_counter[1] ^ jam_counter[3];
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end
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end
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// Antenna drivers
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@ -303,22 +303,22 @@ begin
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pwr_oe4 = 1'b0;
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_SEND_JAM)
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begin
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begin
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pwr_hi = ck_1356meg & jam_signal;
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pwr_oe4 = 1'b0;
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ
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|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE
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|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE)
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begin // all off
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pwr_hi = 1'b0;
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pwr_oe4 = 1'b0;
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end
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else // receiving from tag
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begin
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pwr_hi = ck_1356meg;
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pwr_oe4 = 1'b0;
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end
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ
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|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE
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|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE)
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begin // all off
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pwr_hi = 1'b0;
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pwr_oe4 = 1'b0;
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end
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else // receiving from tag
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begin
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pwr_hi = ck_1356meg;
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pwr_oe4 = 1'b0;
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end
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end
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// always on
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