github/RRG-Proxmark3
1
0
Fork 0
mirror of https://github.com/RfidResearchGroup/proxmark3.git synced 2025-08-21 13:53:55 -07:00
Code Issues Projects Releases Packages Wiki Activity Actions

style

Browse source
This commit is contained in:
iceman1001 2020-01-12 00:18:34 +01:00
commit 442bab0706
1 changed files with 19 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

21
fpga/hi_get_trace.v
View file

@ -77,9 +77,11 @@ begin
write_enable2 <= 1'b0; write_enable2 <= 1'b0;
end end
else else
begin
addr <= addr + 1; addr <= addr + 1;
end end
end end
end
else else
begin begin
write_enable1 <= 1'b0; write_enable1 <= 1'b0;
@ -92,15 +94,17 @@ begin
write_enable1 <= 1'b0; write_enable1 <= 1'b0;
write_enable2 <= 1'b0; write_enable2 <= 1'b0;
if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
begin
start_addr <= addr; start_addr <= addr;
end end
end
end end
// (2+1)k RAM // (2+1)k RAM
reg [7:0] D_out1, D_out2; reg [7:0] D_out1, D_out2;
reg [7:0] ram1 [2047:0]; reg [7:0] ram1 [2047:0]; // 2048 u8
reg [7:0] ram2 [1023:0]; reg [7:0] ram2 [1023:0]; // 1024 u8
always @(negedge ck_1356megb) always @(negedge ck_1356megb)
begin begin
@ -112,7 +116,7 @@ begin
else else
D_out1 <= ram1[addr[10:0]]; D_out1 <= ram1[addr[10:0]];
if (write_enable2) if (write_enable2)
begin begin
ram2[addr[9:0]] <= adc_d; ram2[addr[9:0]] <= adc_d;
D_out2 <= adc_d; D_out2 <= adc_d;
end end
@ -128,22 +132,25 @@ reg [7:0] shift_out;
always @(negedge ck_1356megb) always @(negedge ck_1356megb)
begin begin
if(clock_cnt[3:0] == 4'd0) // update shift register every 16 clock cycles if (clock_cnt[3:0] == 4'd0) // update shift register every 16 clock cycles
begin begin
if(clock_cnt[6:4] == 3'd0) // either load new value if (clock_cnt[6:4] == 3'd0) // either load new value
begin begin
if (addr[11] == 1'b0) if (addr[11] == 1'b0)
shift_out <= D_out1; shift_out <= D_out1;
else else
shift_out <= D_out2; shift_out <= D_out2;
end end
else // or shift left else
begin
// or shift left
shift_out[7:1] <= shift_out[6:0]; shift_out[7:1] <= shift_out[6:0];
end end
end
ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz
if(clock_cnt[6:4] == 3'b000) // set ssp_frame for 0...31 if (clock_cnt[6:4] == 3'b000) // set ssp_frame for 0...31
ssp_frame <= 1'b1; ssp_frame <= 1'b1;
else else
ssp_frame <= 1'b0; ssp_frame <= 1'b0;