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This commit is contained in:
iceman1001 2020-01-12 00:18:34 +01:00
commit 442bab0706
1 changed files with 19 additions and 12 deletions
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13
fpga/hi_get_trace.v
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@ -77,9 +77,11 @@ begin
write_enable2 <= 1'b0; write_enable2 <= 1'b0;
end end
else else
begin
addr <= addr + 1; addr <= addr + 1;
end end
end end
end
else else
begin begin
write_enable1 <= 1'b0; write_enable1 <= 1'b0;
@ -92,15 +94,17 @@ begin
write_enable1 <= 1'b0; write_enable1 <= 1'b0;
write_enable2 <= 1'b0; write_enable2 <= 1'b0;
if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
begin
start_addr <= addr; start_addr <= addr;
end end
end end
end
// (2+1)k RAM // (2+1)k RAM
reg [7:0] D_out1, D_out2; reg [7:0] D_out1, D_out2;
reg [7:0] ram1 [2047:0]; reg [7:0] ram1 [2047:0]; // 2048 u8
reg [7:0] ram2 [1023:0]; reg [7:0] ram2 [1023:0]; // 1024 u8
always @(negedge ck_1356megb) always @(negedge ck_1356megb)
begin begin
@ -137,9 +141,12 @@ begin
else else
shift_out <= D_out2; shift_out <= D_out2;
end end
else // or shift left else
begin
// or shift left
shift_out[7:1] <= shift_out[6:0]; shift_out[7:1] <= shift_out[6:0];
end end
end
ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz