mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-21 05:43:48 -07:00
Merge pull request #2473 from douniwan5788/prune
Fixes and improve SKIP_* directives
This commit is contained in:
commit
42c873f49c
21 changed files with 173 additions and 115 deletions
|
@ -3,6 +3,7 @@ All notable changes to this project will be documented in this file.
|
||||||
This project uses the changelog in accordance with [keepchangelog](http://keepachangelog.com/). Please use this to write notable changes, which is not the same as git commit log...
|
This project uses the changelog in accordance with [keepchangelog](http://keepachangelog.com/). Please use this to write notable changes, which is not the same as git commit log...
|
||||||
|
|
||||||
## [unreleased][unreleased]
|
## [unreleased][unreleased]
|
||||||
|
- Firmware size optimization, skipping unused FPGA bitstreams (@douniwan5788)
|
||||||
- Added pretty Hitag S config parsing (@CiRIP)
|
- Added pretty Hitag S config parsing (@CiRIP)
|
||||||
- Moved Hitag S operations into separate submenu: `lf hitag s` (@CiRIP)
|
- Moved Hitag S operations into separate submenu: `lf hitag s` (@CiRIP)
|
||||||
- Added MFC keys for Sofia public transport cards (@user890104)
|
- Added MFC keys for Sofia public transport cards (@user890104)
|
||||||
|
|
|
@ -20,12 +20,21 @@ PLATFORM=PM3RDV4
|
||||||
#PLATFORM=PM3GENERIC
|
#PLATFORM=PM3GENERIC
|
||||||
#PLATFORM_SIZE=256
|
#PLATFORM_SIZE=256
|
||||||
#STANDALONE=
|
#STANDALONE=
|
||||||
#SKIP_HITAG=1
|
|
||||||
#SKIP_FELICA=1
|
|
||||||
#SKIP_HFPLOT=1
|
|
||||||
#SKIP_NFCBARCODE=1
|
|
||||||
#SKIP_ZX8211=1
|
|
||||||
#SKIP_LF=1
|
#SKIP_LF=1
|
||||||
|
#SKIP_HITAG=1
|
||||||
|
#SKIP_EM4x50=1
|
||||||
|
#SKIP_EM4x70=1
|
||||||
|
#SKIP_ZX8211=1
|
||||||
|
#SKIP_HF=1
|
||||||
|
#SKIP_ISO15693=1
|
||||||
|
#SKIP_LEGICRF=1
|
||||||
|
#SKIP_ISO14443b=1
|
||||||
|
#SKIP_ISO14443a=1
|
||||||
|
#SKIP_ICLASS=1
|
||||||
|
#SKIP_FELICA=1
|
||||||
|
#SKIP_NFCBARCODE=1
|
||||||
|
#SKIP_HFSNIFF=1
|
||||||
|
#SKIP_HFPLOT=1
|
||||||
|
|
||||||
# To accelerate repetitive compilations:
|
# To accelerate repetitive compilations:
|
||||||
# Install package "ccache" -> Debian/Ubuntu: /usr/lib/ccache, Fedora/CentOS/RHEL: /usr/lib64/ccache
|
# Install package "ccache" -> Debian/Ubuntu: /usr/lib/ccache, Fedora/CentOS/RHEL: /usr/lib64/ccache
|
||||||
|
|
|
@ -162,7 +162,7 @@ uint16_t SumAdc(uint8_t ch, uint8_t NbSamples) {
|
||||||
a += ReadAdc(ch);
|
a += ReadAdc(ch);
|
||||||
return (a + (NbSamples >> 1) - 1);
|
return (a + (NbSamples >> 1) - 1);
|
||||||
}
|
}
|
||||||
|
#ifdef WITH_LF
|
||||||
static void MeasureAntennaTuning(void) {
|
static void MeasureAntennaTuning(void) {
|
||||||
|
|
||||||
uint32_t peak = 0;
|
uint32_t peak = 0;
|
||||||
|
@ -236,7 +236,7 @@ static void MeasureAntennaTuning(void) {
|
||||||
reply_ng(CMD_MEASURE_ANTENNA_TUNING, PM3_SUCCESS, (uint8_t *)&payload, sizeof(payload));
|
reply_ng(CMD_MEASURE_ANTENNA_TUNING, PM3_SUCCESS, (uint8_t *)&payload, sizeof(payload));
|
||||||
LEDsoff();
|
LEDsoff();
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
// Measure HF in milliVolt
|
// Measure HF in milliVolt
|
||||||
static uint16_t MeasureAntennaTuningHfData(void) {
|
static uint16_t MeasureAntennaTuningHfData(void) {
|
||||||
|
|
||||||
|
@ -306,7 +306,7 @@ static void SendVersion(void) {
|
||||||
strncat(VersionString, "\n [ "_YELLOW_("FPGA")" ] \n ", sizeof(VersionString) - strlen(VersionString) - 1);
|
strncat(VersionString, "\n [ "_YELLOW_("FPGA")" ] \n ", sizeof(VersionString) - strlen(VersionString) - 1);
|
||||||
|
|
||||||
for (int i = 0; i < g_fpga_bitstream_num; i++) {
|
for (int i = 0; i < g_fpga_bitstream_num; i++) {
|
||||||
strncat(VersionString, g_fpga_version_information[i], sizeof(VersionString) - strlen(VersionString) - 1);
|
strncat(VersionString, g_fpga_version_information[i].versionString, sizeof(VersionString) - strlen(VersionString) - 1);
|
||||||
if (i < g_fpga_bitstream_num - 1) {
|
if (i < g_fpga_bitstream_num - 1) {
|
||||||
strncat(VersionString, "\n ", sizeof(VersionString) - strlen(VersionString) - 1);
|
strncat(VersionString, "\n ", sizeof(VersionString) - strlen(VersionString) - 1);
|
||||||
}
|
}
|
||||||
|
@ -1610,7 +1610,9 @@ static void PacketReceived(PacketCommandNG *packet) {
|
||||||
struct p *payload = (struct p *) packet->data.asBytes;
|
struct p *payload = (struct p *) packet->data.asBytes;
|
||||||
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
||||||
FpgaSendCommand(FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, (payload->threshold & 0x3f) | ((payload->threshold_high & 0x3f) << 6));
|
FpgaSendCommand(FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, (payload->threshold & 0x3f) | ((payload->threshold_high & 0x3f) << 6));
|
||||||
|
#ifdef WITH_LEGICRF
|
||||||
LegicRfSetThreshold((uint32_t)payload->legic_threshold);
|
LegicRfSetThreshold((uint32_t)payload->legic_threshold);
|
||||||
|
#endif
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case CMD_HF_ISO14443A_SNIFF: {
|
case CMD_HF_ISO14443A_SNIFF: {
|
||||||
|
@ -2301,10 +2303,12 @@ static void PacketReceived(PacketCommandNG *packet) {
|
||||||
BigBuf_free();
|
BigBuf_free();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
#ifdef WITH_LF
|
||||||
case CMD_MEASURE_ANTENNA_TUNING: {
|
case CMD_MEASURE_ANTENNA_TUNING: {
|
||||||
MeasureAntennaTuning();
|
MeasureAntennaTuning();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
case CMD_MEASURE_ANTENNA_TUNING_HF: {
|
case CMD_MEASURE_ANTENNA_TUNING_HF: {
|
||||||
if (packet->length != 1)
|
if (packet->length != 1)
|
||||||
reply_ng(CMD_MEASURE_ANTENNA_TUNING_HF, PM3_EINVARG, NULL, 0);
|
reply_ng(CMD_MEASURE_ANTENNA_TUNING_HF, PM3_EINVARG, NULL, 0);
|
||||||
|
@ -2394,12 +2398,8 @@ static void PacketReceived(PacketCommandNG *packet) {
|
||||||
Dbprintf("transfer to client failed :: | bytes between %d - %d (%d) | result: %d", i, i + len, len, result);
|
Dbprintf("transfer to client failed :: | bytes between %d - %d (%d) | result: %d", i, i + len, len, result);
|
||||||
}
|
}
|
||||||
// Trigger a finish downloading signal with an ACK frame
|
// Trigger a finish downloading signal with an ACK frame
|
||||||
// iceman, when did sending samplingconfig array got attached here?!?
|
|
||||||
// arg0 = status of download transfer
|
// arg0 = status of download transfer
|
||||||
// arg1 = RFU
|
reply_mix(CMD_ACK, 1, 0, 0, 0, 0);
|
||||||
// arg2 = tracelen?
|
|
||||||
// asbytes = samplingconfig array
|
|
||||||
reply_mix(CMD_ACK, 1, 0, BigBuf_get_traceLen(), getSamplingConfig(), sizeof(sample_config));
|
|
||||||
LED_B_OFF();
|
LED_B_OFF();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -2818,11 +2818,13 @@ static void PacketReceived(PacketCommandNG *packet) {
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef WITH_LF
|
||||||
case CMD_LF_SET_DIVISOR: {
|
case CMD_LF_SET_DIVISOR: {
|
||||||
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
|
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
|
||||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, packet->data.asBytes[0]);
|
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, packet->data.asBytes[0]);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
case CMD_SET_ADC_MUX: {
|
case CMD_SET_ADC_MUX: {
|
||||||
switch (packet->data.asBytes[0]) {
|
switch (packet->data.asBytes[0]) {
|
||||||
case 0:
|
case 0:
|
||||||
|
|
|
@ -377,7 +377,7 @@ static int bruteforce(const uint8_t address, const uint8_t *rnd, const uint8_t *
|
||||||
uint8_t rev_rnd[7];
|
uint8_t rev_rnd[7];
|
||||||
uint8_t temp_rnd[7];
|
uint8_t temp_rnd[7];
|
||||||
|
|
||||||
reverse_arraycopy((uint8_t *)rnd, rev_rnd, sizeof(rev_rnd));
|
reverse_arraybytes_copy((uint8_t *)rnd, rev_rnd, sizeof(rev_rnd));
|
||||||
memcpy(temp_rnd, rnd, sizeof(temp_rnd));
|
memcpy(temp_rnd, rnd, sizeof(temp_rnd));
|
||||||
|
|
||||||
for (int k = start_key; k <= 0xFFFF; ++k) {
|
for (int k = start_key; k <= 0xFFFF; ++k) {
|
||||||
|
|
|
@ -39,7 +39,7 @@ typedef struct {
|
||||||
typedef lz4_stream_t *lz4_streamp_t;
|
typedef lz4_stream_t *lz4_streamp_t;
|
||||||
|
|
||||||
// remember which version of the bitstream we have already downloaded to the FPGA
|
// remember which version of the bitstream we have already downloaded to the FPGA
|
||||||
static int downloaded_bitstream = 0;
|
static int downloaded_bitstream = FPGA_BITSTREAM_UNKNOWN;
|
||||||
|
|
||||||
// this is where the bitstreams are located in memory:
|
// this is where the bitstreams are located in memory:
|
||||||
extern uint32_t _binary_obj_fpga_all_bit_z_start[], _binary_obj_fpga_all_bit_z_end[];
|
extern uint32_t _binary_obj_fpga_all_bit_z_start[], _binary_obj_fpga_all_bit_z_end[];
|
||||||
|
@ -221,14 +221,31 @@ static int get_from_fpga_combined_stream(lz4_streamp_t compressed_fpga_stream, u
|
||||||
return *fpga_image_ptr++;
|
return *fpga_image_ptr++;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int bitstream_target_to_index(FPGA_config bitstream_target) {
|
||||||
|
static int8_t bitstream_index_map[FPGA_BITSTREAM_MAX] = {-1};
|
||||||
|
|
||||||
|
// Initialize
|
||||||
|
if (bitstream_index_map[0] == -1){
|
||||||
|
bitstream_index_map[0] = 0;
|
||||||
|
|
||||||
|
for (size_t i = 0; i < g_fpga_bitstream_num; i++) {
|
||||||
|
FPGA_VERSION_INFORMATION info = g_fpga_version_information[i];
|
||||||
|
bitstream_index_map[info.target_config] = i;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstream_index_map[bitstream_target];
|
||||||
|
}
|
||||||
|
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
// Undo the interleaving of several FPGA config files. FPGA config files
|
// Undo the interleaving of several FPGA config files. FPGA config files
|
||||||
// are combined into one big file:
|
// are combined into one big file:
|
||||||
// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
|
// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
static int get_from_fpga_stream(int bitstream_version, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
|
static int get_from_fpga_stream(int bitstream_target, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
|
||||||
while ((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % g_fpga_bitstream_num != (bitstream_version - 1)) {
|
int bitstream_index = bitstream_target_to_index(bitstream_target);
|
||||||
// skip undesired data belonging to other bitstream_versions
|
while ((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % g_fpga_bitstream_num != bitstream_index) {
|
||||||
|
// skip undesired data belonging to other bitstream_targets
|
||||||
get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
|
get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -238,7 +255,7 @@ static int get_from_fpga_stream(int bitstream_version, lz4_streamp_t compressed_
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
// Initialize decompression of the respective (HF or LF) FPGA stream
|
// Initialize decompression of the respective (HF or LF) FPGA stream
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
static bool reset_fpga_stream(int bitstream_version, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
|
static bool reset_fpga_stream(int bitstream_target, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
|
||||||
uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
|
uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
|
||||||
|
|
||||||
uncompressed_bytes_cnt = 0;
|
uncompressed_bytes_cnt = 0;
|
||||||
|
@ -254,7 +271,7 @@ static bool reset_fpga_stream(int bitstream_version, lz4_streamp_t compressed_fp
|
||||||
fpga_image_ptr = output_buffer + FPGA_RING_BUFFER_BYTES;
|
fpga_image_ptr = output_buffer + FPGA_RING_BUFFER_BYTES;
|
||||||
|
|
||||||
for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++)
|
for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++)
|
||||||
header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
header[i] = get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer);
|
||||||
|
|
||||||
// Check for a valid .bit file (starts with bitparse_fixed_header)
|
// Check for a valid .bit file (starts with bitparse_fixed_header)
|
||||||
if (memcmp(bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0)
|
if (memcmp(bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0)
|
||||||
|
@ -276,7 +293,7 @@ static void DownloadFPGA_byte(uint8_t w) {
|
||||||
}
|
}
|
||||||
|
|
||||||
// Download the fpga image starting at current stream position with length FpgaImageLen bytes
|
// Download the fpga image starting at current stream position with length FpgaImageLen bytes
|
||||||
static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
|
static void DownloadFPGA(int bitstream_target, int FpgaImageLen, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
|
||||||
int i = 0;
|
int i = 0;
|
||||||
#if !defined XC3
|
#if !defined XC3
|
||||||
AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
|
AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
|
||||||
|
@ -354,7 +371,7 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
for (i = 0; i < FpgaImageLen; i++) {
|
for (i = 0; i < FpgaImageLen; i++) {
|
||||||
int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
int b = get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer);
|
||||||
if (b < 0) {
|
if (b < 0) {
|
||||||
Dbprintf("Error %d during FpgaDownload", b);
|
Dbprintf("Error %d during FpgaDownload", b);
|
||||||
break;
|
break;
|
||||||
|
@ -383,14 +400,14 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t
|
||||||
* (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
|
* (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
|
||||||
* length.
|
* length.
|
||||||
*/
|
*/
|
||||||
static int bitparse_find_section(int bitstream_version, char section_name, uint32_t *section_length, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
|
static int bitparse_find_section(int bitstream_target, char section_name, uint32_t *section_length, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
|
||||||
|
|
||||||
#define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
|
#define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
|
||||||
|
|
||||||
int result = 0;
|
int result = 0;
|
||||||
uint16_t numbytes = 0;
|
uint16_t numbytes = 0;
|
||||||
while (numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
|
while (numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
|
||||||
char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
char current_name = get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer);
|
||||||
numbytes++;
|
numbytes++;
|
||||||
uint32_t current_length = 0;
|
uint32_t current_length = 0;
|
||||||
if (current_name < 'a' || current_name > 'e') {
|
if (current_name < 'a' || current_name > 'e') {
|
||||||
|
@ -401,10 +418,10 @@ static int bitparse_find_section(int bitstream_version, char section_name, uint3
|
||||||
switch (current_name) {
|
switch (current_name) {
|
||||||
case 'e':
|
case 'e':
|
||||||
/* Four byte length field */
|
/* Four byte length field */
|
||||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
|
current_length += get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer) << 24;
|
||||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
|
current_length += get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer) << 16;
|
||||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
|
current_length += get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer) << 8;
|
||||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
|
current_length += get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer) << 0;
|
||||||
numbytes += 4;
|
numbytes += 4;
|
||||||
if (current_length > 300 * 1024) {
|
if (current_length > 300 * 1024) {
|
||||||
/* section e should never exceed about 300KB, if the length is too big limit it but still send the bitstream just in case */
|
/* section e should never exceed about 300KB, if the length is too big limit it but still send the bitstream just in case */
|
||||||
|
@ -412,8 +429,8 @@ static int bitparse_find_section(int bitstream_version, char section_name, uint3
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
default: /* Two byte length field */
|
default: /* Two byte length field */
|
||||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
|
current_length += get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer) << 8;
|
||||||
current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
|
current_length += get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer) << 0;
|
||||||
numbytes += 2;
|
numbytes += 2;
|
||||||
if (current_length > 64) {
|
if (current_length > 64) {
|
||||||
/* if text field is too long, keep it but truncate it */
|
/* if text field is too long, keep it but truncate it */
|
||||||
|
@ -429,7 +446,7 @@ static int bitparse_find_section(int bitstream_version, char section_name, uint3
|
||||||
}
|
}
|
||||||
|
|
||||||
for (uint32_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
|
for (uint32_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
|
||||||
get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
|
get_from_fpga_stream(bitstream_target, compressed_fpga_stream, output_buffer);
|
||||||
numbytes++;
|
numbytes++;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -438,16 +455,16 @@ static int bitparse_find_section(int bitstream_version, char section_name, uint3
|
||||||
|
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
// Change FPGA image status, if image loaded.
|
// Change FPGA image status, if image loaded.
|
||||||
// bitstream_version is your new fpga image version
|
// bitstream_target is your new fpga image version
|
||||||
// return true if can change.
|
// return true if can change.
|
||||||
// return false if image is unloaded.
|
// return false if image is unloaded.
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
#if defined XC3
|
#if defined XC3
|
||||||
static bool FpgaConfCurrentMode(int bitstream_version) {
|
static bool FpgaConfCurrentMode(int bitstream_target) {
|
||||||
// fpga "XC3S100E" image merge
|
// fpga "XC3S100E" image merge
|
||||||
// If fpga image is no init
|
// If fpga image is no init
|
||||||
// We need load hf_lf_allinone.bit
|
// We need load hf_lf_allinone.bit
|
||||||
if (downloaded_bitstream != 0) {
|
if (downloaded_bitstream != FPGA_BITSTREAM_UNKNOWN) {
|
||||||
// test start
|
// test start
|
||||||
// PIO controls the following pins
|
// PIO controls the following pins
|
||||||
AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_SWITCH;
|
AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_SWITCH;
|
||||||
|
@ -457,13 +474,13 @@ static bool FpgaConfCurrentMode(int bitstream_version) {
|
||||||
// try to turn off antenna
|
// try to turn off antenna
|
||||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||||
|
|
||||||
if (bitstream_version == FPGA_BITSTREAM_LF) {
|
if (bitstream_target == FPGA_BITSTREAM_LF) {
|
||||||
LOW(GPIO_FPGA_SWITCH);
|
LOW(GPIO_FPGA_SWITCH);
|
||||||
} else {
|
} else {
|
||||||
HIGH(GPIO_FPGA_SWITCH);
|
HIGH(GPIO_FPGA_SWITCH);
|
||||||
}
|
}
|
||||||
// update downloaded_bitstream
|
// update downloaded_bitstream
|
||||||
downloaded_bitstream = bitstream_version;
|
downloaded_bitstream = bitstream_target;
|
||||||
// turn off antenna
|
// turn off antenna
|
||||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||||
return true;
|
return true;
|
||||||
|
@ -476,10 +493,10 @@ static bool FpgaConfCurrentMode(int bitstream_version) {
|
||||||
// Check which FPGA image is currently loaded (if any). If necessary
|
// Check which FPGA image is currently loaded (if any). If necessary
|
||||||
// decompress and load the correct (HF or LF) image to the FPGA
|
// decompress and load the correct (HF or LF) image to the FPGA
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
void FpgaDownloadAndGo(int bitstream_version) {
|
void FpgaDownloadAndGo(int bitstream_target) {
|
||||||
|
|
||||||
// check whether or not the bitstream is already loaded
|
// check whether or not the bitstream is already loaded
|
||||||
if (downloaded_bitstream == bitstream_version) {
|
if (downloaded_bitstream == bitstream_target) {
|
||||||
FpgaEnableTracing();
|
FpgaEnableTracing();
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -487,7 +504,7 @@ void FpgaDownloadAndGo(int bitstream_version) {
|
||||||
#if defined XC3
|
#if defined XC3
|
||||||
// If we can change image version
|
// If we can change image version
|
||||||
// direct return.
|
// direct return.
|
||||||
if (FpgaConfCurrentMode(bitstream_version)) {
|
if (FpgaConfCurrentMode(bitstream_target)) {
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -506,19 +523,19 @@ void FpgaDownloadAndGo(int bitstream_version) {
|
||||||
compressed_fpga_stream.lz4StreamDecode = &lz4StreamDecode_body;
|
compressed_fpga_stream.lz4StreamDecode = &lz4StreamDecode_body;
|
||||||
uint8_t *output_buffer = BigBuf_malloc(FPGA_RING_BUFFER_BYTES);
|
uint8_t *output_buffer = BigBuf_malloc(FPGA_RING_BUFFER_BYTES);
|
||||||
|
|
||||||
if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer))
|
if (!reset_fpga_stream(bitstream_target, &compressed_fpga_stream, output_buffer))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
uint32_t bitstream_length;
|
uint32_t bitstream_length;
|
||||||
if (bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
|
if (bitparse_find_section(bitstream_target, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
|
||||||
DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
|
DownloadFPGA(bitstream_target, bitstream_length, &compressed_fpga_stream, output_buffer);
|
||||||
downloaded_bitstream = bitstream_version;
|
downloaded_bitstream = bitstream_target;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined XC3
|
#if defined XC3
|
||||||
// first download fpga image to hf
|
// first download fpga image to hf
|
||||||
// we need to change fpga status to hf
|
// we need to change fpga status to hf
|
||||||
FpgaConfCurrentMode(bitstream_version);
|
FpgaConfCurrentMode(bitstream_target);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// turn off antenna
|
// turn off antenna
|
||||||
|
@ -603,7 +620,7 @@ void SetAdcMuxFor(uint32_t whichGpio) {
|
||||||
|
|
||||||
void Fpga_print_status(void) {
|
void Fpga_print_status(void) {
|
||||||
DbpString(_CYAN_("Current FPGA image"));
|
DbpString(_CYAN_("Current FPGA image"));
|
||||||
Dbprintf(" mode....................%s", g_fpga_version_information[downloaded_bitstream - 1]);
|
Dbprintf(" mode.................... %s", g_fpga_version_information[bitstream_target_to_index(downloaded_bitstream)]);
|
||||||
}
|
}
|
||||||
|
|
||||||
int FpgaGetCurrent(void) {
|
int FpgaGetCurrent(void) {
|
||||||
|
|
|
@ -20,6 +20,7 @@
|
||||||
#define __FPGALOADER_H
|
#define __FPGALOADER_H
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
|
#include "fpga.h"
|
||||||
|
|
||||||
#define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
|
#define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
|
||||||
#define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
|
#define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
|
||||||
|
@ -164,8 +165,8 @@ void FpgaSendCommand(uint16_t cmd, uint16_t v);
|
||||||
void FpgaWriteConfWord(uint16_t v);
|
void FpgaWriteConfWord(uint16_t v);
|
||||||
void FpgaEnableTracing(void);
|
void FpgaEnableTracing(void);
|
||||||
void FpgaDisableTracing(void);
|
void FpgaDisableTracing(void);
|
||||||
void FpgaDownloadAndGo(int bitstream_version);
|
void FpgaDownloadAndGo(int bitstream_target);
|
||||||
// void FpgaGatherVersion(int bitstream_version, char *dst, int len);
|
// void FpgaGatherVersion(int bitstream_target, char *dst, int len);
|
||||||
void FpgaSetupSsc(uint16_t fpga_mode);
|
void FpgaSetupSsc(uint16_t fpga_mode);
|
||||||
void SetupSpi(int mode);
|
void SetupSpi(int mode);
|
||||||
bool FpgaSetupSscDma(uint8_t *buf, uint16_t len);
|
bool FpgaSetupSscDma(uint8_t *buf, uint16_t len);
|
||||||
|
|
|
@ -114,24 +114,3 @@ uint64_t x_bytes_to_num(uint8_t *src, size_t len) {
|
||||||
return num;
|
return num;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t reversebyte(uint8_t b) {
|
|
||||||
b = (b & 0xF0) >> 4 | (b & 0x0F) << 4;
|
|
||||||
b = (b & 0xCC) >> 2 | (b & 0x33) << 2;
|
|
||||||
b = (b & 0xAA) >> 1 | (b & 0x55) << 1;
|
|
||||||
return b;
|
|
||||||
}
|
|
||||||
|
|
||||||
void reverse_arraybytes(uint8_t *arr, size_t len) {
|
|
||||||
size_t i;
|
|
||||||
for (i = 0; i < len ; i++) {
|
|
||||||
arr[i] = reversebyte(arr[i]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void reverse_arraycopy(uint8_t *arr, uint8_t *dest, size_t len) {
|
|
||||||
size_t i;
|
|
||||||
for (i = 0; i < len ; i++) {
|
|
||||||
dest[i] = reversebyte(arr[i]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
|
@ -57,7 +57,4 @@ int bitsLeft(BitstreamIn_t *stream);
|
||||||
void push6bits(BitstreamOut_t *stream, uint8_t bits);
|
void push6bits(BitstreamOut_t *stream, uint8_t bits);
|
||||||
void x_num_to_bytes(uint64_t n, size_t len, uint8_t *dest);
|
void x_num_to_bytes(uint64_t n, size_t len, uint8_t *dest);
|
||||||
uint64_t x_bytes_to_num(uint8_t *src, size_t len);
|
uint64_t x_bytes_to_num(uint8_t *src, size_t len);
|
||||||
uint8_t reversebyte(uint8_t b);
|
|
||||||
void reverse_arraybytes(uint8_t *arr, size_t len);
|
|
||||||
void reverse_arraycopy(uint8_t *arr, uint8_t *dest, size_t len);
|
|
||||||
#endif // CIPHERUTILS_H
|
#endif // CIPHERUTILS_H
|
||||||
|
|
|
@ -44,6 +44,7 @@
|
||||||
#include "preferences.h"
|
#include "preferences.h"
|
||||||
#include "mifare/gen4.h"
|
#include "mifare/gen4.h"
|
||||||
#include "generator.h" // keygens.
|
#include "generator.h" // keygens.
|
||||||
|
#include "fpga.h"
|
||||||
|
|
||||||
static int CmdHelp(const char *Cmd);
|
static int CmdHelp(const char *Cmd);
|
||||||
|
|
||||||
|
|
|
@ -1468,12 +1468,12 @@ static command_t CommandTable[] = {
|
||||||
{"ping", CmdPing, IfPm3Present, "Test if the Proxmark3 is responsive"},
|
{"ping", CmdPing, IfPm3Present, "Test if the Proxmark3 is responsive"},
|
||||||
{"readmem", CmdReadmem, IfPm3Present, "Read from MCU flash"},
|
{"readmem", CmdReadmem, IfPm3Present, "Read from MCU flash"},
|
||||||
{"reset", CmdReset, IfPm3Present, "Reset the device"},
|
{"reset", CmdReset, IfPm3Present, "Reset the device"},
|
||||||
{"setlfdivisor", CmdSetDivisor, IfPm3Present, "Drive LF antenna at 12MHz / (divisor + 1)"},
|
{"setlfdivisor", CmdSetDivisor, IfPm3Lf, "Drive LF antenna at 12MHz / (divisor + 1)"},
|
||||||
{"sethfthresh", CmdSetHFThreshold, IfPm3Present, "Set thresholds in HF/14a mode"},
|
{"sethfthresh", CmdSetHFThreshold, IfPm3Iso14443a, "Set thresholds in HF/14a mode"},
|
||||||
{"setmux", CmdSetMux, IfPm3Present, "Set the ADC mux to a specific value"},
|
{"setmux", CmdSetMux, IfPm3Present, "Set the ADC mux to a specific value"},
|
||||||
{"standalone", CmdStandalone, IfPm3Present, "Start installed standalone mode on device"},
|
{"standalone", CmdStandalone, IfPm3Present, "Start installed standalone mode on device"},
|
||||||
{"tia", CmdTia, IfPm3Present, "Trigger a Timing Interval Acquisition to re-adjust the RealTimeCounter divider"},
|
{"tia", CmdTia, IfPm3Present, "Trigger a Timing Interval Acquisition to re-adjust the RealTimeCounter divider"},
|
||||||
{"tune", CmdTune, IfPm3Present, "Measure tuning of device antenna"},
|
{"tune", CmdTune, IfPm3Lf, "Measure tuning of device antenna"},
|
||||||
{NULL, NULL, NULL, NULL}
|
{NULL, NULL, NULL, NULL}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -67,6 +67,7 @@
|
||||||
#include "cmdlfzx8211.h" // for ZX8211 menu
|
#include "cmdlfzx8211.h" // for ZX8211 menu
|
||||||
#include "crc.h"
|
#include "crc.h"
|
||||||
#include "pm3_cmd.h" // for LF_CMDREAD_MAX_EXTRA_SYMBOLS
|
#include "pm3_cmd.h" // for LF_CMDREAD_MAX_EXTRA_SYMBOLS
|
||||||
|
#include "fpga.h" // for set_fpga_mode
|
||||||
|
|
||||||
static int CmdHelp(const char *Cmd);
|
static int CmdHelp(const char *Cmd);
|
||||||
|
|
||||||
|
@ -1552,7 +1553,7 @@ static bool check_chiptype(bool getDeviceData) {
|
||||||
|
|
||||||
//check for em4x05/em4x69 chips first
|
//check for em4x05/em4x69 chips first
|
||||||
uint32_t word = 0;
|
uint32_t word = 0;
|
||||||
if (em4x05_isblock0(&word)) {
|
if (IfPm3EM4x50() && em4x05_isblock0(&word)) {
|
||||||
PrintAndLogEx(SUCCESS, "Chipset detection: " _GREEN_("EM4x05 / EM4x69"));
|
PrintAndLogEx(SUCCESS, "Chipset detection: " _GREEN_("EM4x05 / EM4x69"));
|
||||||
PrintAndLogEx(HINT, "Hint: try " _YELLOW_("`lf em 4x05`") " commands");
|
PrintAndLogEx(HINT, "Hint: try " _YELLOW_("`lf em 4x05`") " commands");
|
||||||
retval = true;
|
retval = true;
|
||||||
|
@ -1569,7 +1570,7 @@ static bool check_chiptype(bool getDeviceData) {
|
||||||
|
|
||||||
#if !defined ICOPYX
|
#if !defined ICOPYX
|
||||||
// check for em4x50 chips
|
// check for em4x50 chips
|
||||||
if (detect_4x50_block()) {
|
if (IfPm3EM4x50() && detect_4x50_block()) {
|
||||||
PrintAndLogEx(SUCCESS, "Chipset detection: " _GREEN_("EM4x50"));
|
PrintAndLogEx(SUCCESS, "Chipset detection: " _GREEN_("EM4x50"));
|
||||||
PrintAndLogEx(HINT, "Hint: try " _YELLOW_("`lf em 4x50`") " commands");
|
PrintAndLogEx(HINT, "Hint: try " _YELLOW_("`lf em 4x50`") " commands");
|
||||||
retval = true;
|
retval = true;
|
||||||
|
@ -1577,7 +1578,7 @@ static bool check_chiptype(bool getDeviceData) {
|
||||||
}
|
}
|
||||||
|
|
||||||
// check for em4x70 chips
|
// check for em4x70 chips
|
||||||
if (detect_4x70_block()) {
|
if (IfPm3EM4x70() && detect_4x70_block()) {
|
||||||
PrintAndLogEx(SUCCESS, "Chipset detection: " _GREEN_("EM4x70"));
|
PrintAndLogEx(SUCCESS, "Chipset detection: " _GREEN_("EM4x70"));
|
||||||
PrintAndLogEx(HINT, "Hint: try " _YELLOW_("`lf em 4x70`") " commands");
|
PrintAndLogEx(HINT, "Hint: try " _YELLOW_("`lf em 4x70`") " commands");
|
||||||
retval = true;
|
retval = true;
|
||||||
|
|
|
@ -34,6 +34,7 @@
|
||||||
|
|
||||||
#include "cipher.h"
|
#include "cipher.h"
|
||||||
#include "cipherutils.h"
|
#include "cipherutils.h"
|
||||||
|
#include "commonutil.h"
|
||||||
#include <stdlib.h>
|
#include <stdlib.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <stdbool.h>
|
#include <stdbool.h>
|
||||||
|
|
|
@ -125,18 +125,6 @@ uint64_t x_bytes_to_num(uint8_t *src, size_t len) {
|
||||||
return num;
|
return num;
|
||||||
}
|
}
|
||||||
|
|
||||||
void reverse_arraybytes(uint8_t *arr, size_t len) {
|
|
||||||
for (size_t i = 0; i < len ; i++) {
|
|
||||||
arr[i] = reflect8(arr[i]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void reverse_arraycopy(uint8_t *arr, uint8_t *dest, size_t len) {
|
|
||||||
for (size_t i = 0; i < len ; i++) {
|
|
||||||
dest[i] = reflect8(arr[i]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void printarr(const char *name, uint8_t *arr, int len) {
|
void printarr(const char *name, uint8_t *arr, int len) {
|
||||||
if (name == NULL || arr == NULL) return;
|
if (name == NULL || arr == NULL) return;
|
||||||
|
|
||||||
|
|
|
@ -62,9 +62,6 @@ int testCipherUtils(void);
|
||||||
void push6bits(BitstreamOut_t *stream, uint8_t bits);
|
void push6bits(BitstreamOut_t *stream, uint8_t bits);
|
||||||
void x_num_to_bytes(uint64_t n, size_t len, uint8_t *dest);
|
void x_num_to_bytes(uint64_t n, size_t len, uint8_t *dest);
|
||||||
uint64_t x_bytes_to_num(uint8_t *src, size_t len);
|
uint64_t x_bytes_to_num(uint8_t *src, size_t len);
|
||||||
uint8_t reversebyte(uint8_t b);
|
|
||||||
void reverse_arraybytes(uint8_t *arr, size_t len);
|
|
||||||
void reverse_arraycopy(uint8_t *arr, uint8_t *dest, size_t len);
|
|
||||||
void printarr(const char *name, uint8_t *arr, int len);
|
void printarr(const char *name, uint8_t *arr, int len);
|
||||||
void printarr_human_readable(const char *title, uint8_t *arr, int len);
|
void printarr_human_readable(const char *title, uint8_t *arr, int len);
|
||||||
#endif // CIPHERUTILS_H
|
#endif // CIPHERUTILS_H
|
||||||
|
|
|
@ -549,3 +549,17 @@ bool hexstr_to_byte_array(const char *hexstr, uint8_t *d, size_t *n) {
|
||||||
}
|
}
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void reverse_arraybytes(uint8_t *arr, size_t len) {
|
||||||
|
size_t i;
|
||||||
|
for (i = 0; i < len ; i++) {
|
||||||
|
arr[i] = reflect8(arr[i]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void reverse_arraybytes_copy(uint8_t *arr, uint8_t *dest, size_t len) {
|
||||||
|
size_t i;
|
||||||
|
for (i = 0; i < len ; i++) {
|
||||||
|
dest[i] = reflect8(arr[i]);
|
||||||
|
}
|
||||||
|
}
|
|
@ -130,4 +130,7 @@ void reverse_array(uint8_t *d, size_t n);
|
||||||
void reverse_array_copy(const uint8_t *src, int src_len, uint8_t *dest);
|
void reverse_array_copy(const uint8_t *src, int src_len, uint8_t *dest);
|
||||||
|
|
||||||
bool hexstr_to_byte_array(const char *hexstr, uint8_t *d, size_t *n);
|
bool hexstr_to_byte_array(const char *hexstr, uint8_t *d, size_t *n);
|
||||||
|
|
||||||
|
void reverse_arraybytes(uint8_t *arr, size_t len);
|
||||||
|
void reverse_arraybytes_copy(uint8_t *arr, uint8_t *dest, size_t len);
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -73,6 +73,7 @@ and you can specify which parts to skip in order to reduce the size:
|
||||||
SKIP_LF=1
|
SKIP_LF=1
|
||||||
SKIP_HITAG=1
|
SKIP_HITAG=1
|
||||||
SKIP_EM4x50=1
|
SKIP_EM4x50=1
|
||||||
|
SKIP_EM4x70=1
|
||||||
SKIP_ISO15693=1
|
SKIP_ISO15693=1
|
||||||
SKIP_LEGICRF=1
|
SKIP_LEGICRF=1
|
||||||
SKIP_ISO14443b=1
|
SKIP_ISO14443b=1
|
||||||
|
@ -96,32 +97,59 @@ PLTNAME = Unknown Platform
|
||||||
PLATFORM_FPGA = fpga-undefined
|
PLATFORM_FPGA = fpga-undefined
|
||||||
|
|
||||||
ifeq ($(PLATFORM),PM3RDV4)
|
ifeq ($(PLATFORM),PM3RDV4)
|
||||||
# FPGA bitstream files, the order matters!
|
# FPGA bitstream files, the order doesn't matter anymore
|
||||||
FPGA_BITSTREAMS = fpga_pm3_lf.bit fpga_pm3_hf.bit fpga_pm3_felica.bit fpga_pm3_hf_15.bit
|
FPGA_BITSTREAMS = fpga_pm3_hf.bit
|
||||||
|
ifneq ($(SKIP_LF),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_lf.bit
|
||||||
|
endif
|
||||||
|
ifneq ($(SKIP_FELICA),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_felica.bit
|
||||||
|
endif
|
||||||
|
ifneq ($(SKIP_ISO15693),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_hf_15.bit
|
||||||
|
endif
|
||||||
PLATFORM_DEFS = -DWITH_SMARTCARD -DWITH_FLASH -DRDV4
|
PLATFORM_DEFS = -DWITH_SMARTCARD -DWITH_FLASH -DRDV4
|
||||||
PLTNAME = Proxmark3 RDV4
|
PLTNAME = Proxmark3 RDV4
|
||||||
PLATFORM_FPGA = xc2s30
|
PLATFORM_FPGA = xc2s30
|
||||||
RDV4 = yes
|
RDV4 = yes
|
||||||
else ifeq ($(PLATFORM),PM3OTHER)
|
else ifeq ($(PLATFORM),PM3OTHER)
|
||||||
$(warning PLATFORM=PM3OTHER is deprecated, please use PLATFORM=PM3GENERIC)
|
$(warning PLATFORM=PM3OTHER is deprecated, please use PLATFORM=PM3GENERIC)
|
||||||
# FPGA bitstream files, the order matters!
|
# FPGA bitstream files, the order doesn't matter anymore
|
||||||
FPGA_BITSTREAMS = fpga_pm3_lf.bit fpga_pm3_hf.bit fpga_pm3_felica.bit fpga_pm3_hf_15.bit
|
FPGA_BITSTREAMS = fpga_pm3_hf.bit
|
||||||
|
ifneq ($(SKIP_LF),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_lf.bit
|
||||||
|
endif
|
||||||
|
ifneq ($(SKIP_FELICA),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_felica.bit
|
||||||
|
endif
|
||||||
|
ifneq ($(SKIP_ISO15693),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_hf_15.bit
|
||||||
|
endif
|
||||||
PLTNAME = Proxmark3 generic target
|
PLTNAME = Proxmark3 generic target
|
||||||
PLATFORM_FPGA = xc2s30
|
PLATFORM_FPGA = xc2s30
|
||||||
ifeq ($(LED_ORDER),PM3EASY)
|
ifeq ($(LED_ORDER),PM3EASY)
|
||||||
PLATFORM_DEFS = -DLED_ORDER_PM3EASY
|
PLATFORM_DEFS = -DLED_ORDER_PM3EASY
|
||||||
endif
|
endif
|
||||||
else ifeq ($(PLATFORM),PM3GENERIC)
|
else ifeq ($(PLATFORM),PM3GENERIC)
|
||||||
# FPGA bitstream files, the order matters!
|
# FPGA bitstream files, the order doesn't matter anymore
|
||||||
FPGA_BITSTREAMS = fpga_pm3_lf.bit fpga_pm3_hf.bit fpga_pm3_felica.bit fpga_pm3_hf_15.bit
|
FPGA_BITSTREAMS = fpga_pm3_hf.bit
|
||||||
|
ifneq ($(SKIP_LF),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_lf.bit
|
||||||
|
endif
|
||||||
|
ifneq ($(SKIP_FELICA),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_felica.bit
|
||||||
|
endif
|
||||||
|
ifneq ($(SKIP_ISO15693),1)
|
||||||
|
FPGA_BITSTREAMS += fpga_pm3_hf_15.bit
|
||||||
|
endif
|
||||||
PLTNAME = Proxmark3 generic target
|
PLTNAME = Proxmark3 generic target
|
||||||
PLATFORM_FPGA = xc2s30
|
PLATFORM_FPGA = xc2s30
|
||||||
ifeq ($(LED_ORDER),PM3EASY)
|
ifeq ($(LED_ORDER),PM3EASY)
|
||||||
PLATFORM_DEFS = -DLED_ORDER_PM3EASY
|
PLATFORM_DEFS = -DLED_ORDER_PM3EASY
|
||||||
endif
|
endif
|
||||||
else ifeq ($(PLATFORM),PM3ICOPYX)
|
else ifeq ($(PLATFORM),PM3ICOPYX)
|
||||||
# FPGA bitstream files, the order matters - only hf has a bitstream, the other 3 files are 0 bytes
|
# FPGA bitstream files, the order doesn't matter anymore - only hf has a bitstream
|
||||||
FPGA_BITSTREAMS = fpga_icopyx_lf.bit fpga_icopyx_hf.bit fpga_icopyx_felica.bit fpga_icopyx_hf_15.bit
|
FPGA_BITSTREAMS = fpga_icopyx_hf.bit
|
||||||
PLATFORM_DEFS = -DWITH_FLASH -DICOPYX -DXC3
|
PLATFORM_DEFS = -DWITH_FLASH -DICOPYX -DXC3
|
||||||
PLTNAME = iCopy-X with XC3S100E
|
PLTNAME = iCopy-X with XC3S100E
|
||||||
PLATFORM_FPGA = xc3s100e
|
PLATFORM_FPGA = xc3s100e
|
||||||
|
|
|
@ -32,8 +32,25 @@
|
||||||
#define FPGA_RING_BUFFER_BYTES (1024 * 30)
|
#define FPGA_RING_BUFFER_BYTES (1024 * 30)
|
||||||
#define FPGA_TRACE_SIZE 3072
|
#define FPGA_TRACE_SIZE 3072
|
||||||
|
|
||||||
|
// definitions for multiple FPGA config files support
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
FPGA_BITSTREAM_UNKNOWN = 0,
|
||||||
|
FPGA_BITSTREAM_LF = 1,
|
||||||
|
FPGA_BITSTREAM_HF,
|
||||||
|
FPGA_BITSTREAM_HF_FELICA,
|
||||||
|
FPGA_BITSTREAM_HF_15,
|
||||||
|
FPGA_BITSTREAM_MAX = FPGA_BITSTREAM_HF_15,
|
||||||
|
} FPGA_config;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
const char *const versionString;
|
||||||
|
const FPGA_config target_config;
|
||||||
|
} FPGA_VERSION_INFORMATION;
|
||||||
|
|
||||||
static const uint8_t bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
|
static const uint8_t bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
|
||||||
extern const int g_fpga_bitstream_num;
|
extern const int g_fpga_bitstream_num;
|
||||||
extern const char *const g_fpga_version_information[];
|
extern const FPGA_VERSION_INFORMATION g_fpga_version_information[];
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -182,12 +182,6 @@ work:
|
||||||
$(Q)$(XILINX_TOOLS_PREFIX)par $(VERBOSITY) -w $< $@
|
$(Q)$(XILINX_TOOLS_PREFIX)par $(VERBOSITY) -w $< $@
|
||||||
|
|
||||||
%.bit: %.ncd
|
%.bit: %.ncd
|
||||||
# Hacky hack, make empty files for icopyx
|
|
||||||
if echo "$@" | grep -qi "icopyx"; then \
|
|
||||||
truncate -s0 ../fpga_icopyx_lf.bit; \
|
|
||||||
truncate -s0 ../fpga_icopyx_hf_15.bit; \
|
|
||||||
truncate -s0 ../fpga_icopyx_felica.bit; \
|
|
||||||
fi
|
|
||||||
$(Q)$(RM) $@ $*.drc $*.rbt
|
$(Q)$(RM) $@ $*.drc $*.rbt
|
||||||
$(info [=] BITGEN $@)
|
$(info [=] BITGEN $@)
|
||||||
$(Q)$(XILINX_TOOLS_PREFIX)bitgen $(VERBOSITY) -w $* $@
|
$(Q)$(XILINX_TOOLS_PREFIX)bitgen $(VERBOSITY) -w $* $@
|
||||||
|
|
|
@ -891,11 +891,6 @@ typedef struct {
|
||||||
# define UART_TCP_LOCAL_CLIENT_RX_TIMEOUT_MS 40
|
# define UART_TCP_LOCAL_CLIENT_RX_TIMEOUT_MS 40
|
||||||
# define UART_UDP_LOCAL_CLIENT_RX_TIMEOUT_MS 20
|
# define UART_UDP_LOCAL_CLIENT_RX_TIMEOUT_MS 20
|
||||||
|
|
||||||
// definitions for multiple FPGA config files support
|
|
||||||
#define FPGA_BITSTREAM_LF 1
|
|
||||||
#define FPGA_BITSTREAM_HF 2
|
|
||||||
#define FPGA_BITSTREAM_HF_FELICA 3
|
|
||||||
#define FPGA_BITSTREAM_HF_15 4
|
|
||||||
|
|
||||||
// CMD_DEVICE_INFO response packet has flags in arg[0], flag definitions:
|
// CMD_DEVICE_INFO response packet has flags in arg[0], flag definitions:
|
||||||
/* Whether a bootloader that understands the g_common_area is present */
|
/* Whether a bootloader that understands the g_common_area is present */
|
||||||
|
|
|
@ -420,8 +420,9 @@ static void print_version_info_preamble(FILE *outfile, int num_infiles) {
|
||||||
fprintf(outfile, "// This file is generated by fpga_compress. Don't edit!\n");
|
fprintf(outfile, "// This file is generated by fpga_compress. Don't edit!\n");
|
||||||
fprintf(outfile, "//-----------------------------------------------------------------------------\n");
|
fprintf(outfile, "//-----------------------------------------------------------------------------\n");
|
||||||
fprintf(outfile, "\n\n");
|
fprintf(outfile, "\n\n");
|
||||||
|
fprintf(outfile, "#include \"fpga.h\"\n\n");
|
||||||
fprintf(outfile, "const int g_fpga_bitstream_num = %d;\n", num_infiles);
|
fprintf(outfile, "const int g_fpga_bitstream_num = %d;\n", num_infiles);
|
||||||
fprintf(outfile, "const char *const g_fpga_version_information[%d] = {\n", num_infiles);
|
fprintf(outfile, "const FPGA_VERSION_INFORMATION g_fpga_version_information[%d] = {\n", num_infiles);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int generate_fpga_version_info(FILE *infile[], char *infile_names[], int num_infiles, FILE *outfile) {
|
static int generate_fpga_version_info(FILE *infile[], char *infile_names[], int num_infiles, FILE *outfile) {
|
||||||
|
@ -432,7 +433,19 @@ static int generate_fpga_version_info(FILE *infile[], char *infile_names[], int
|
||||||
|
|
||||||
for (int i = 0; i < num_infiles; i++) {
|
for (int i = 0; i < num_infiles; i++) {
|
||||||
FpgaGatherVersion(infile[i], infile_names[i], version_string, sizeof(version_string));
|
FpgaGatherVersion(infile[i], infile_names[i], version_string, sizeof(version_string));
|
||||||
fprintf(outfile, " \" %s\"", version_string);
|
fprintf(outfile, " { \"%s\"", version_string);
|
||||||
|
|
||||||
|
if (!memcmp("fpga_pm3_lf.ncd", version_string, sizeof("fpga_pm3_lf.ncd") - 1))
|
||||||
|
fprintf(outfile, ", FPGA_BITSTREAM_LF }");
|
||||||
|
else if (!memcmp("fpga_pm3_hf_15.ncd", version_string, sizeof("fpga_pm3_hf_15.ncd") - 1))
|
||||||
|
fprintf(outfile, ", FPGA_BITSTREAM_HF_15 }");
|
||||||
|
else if (!memcmp("fpga_pm3_hf.ncd", version_string, sizeof("fpga_pm3_hf.ncd") - 1))
|
||||||
|
fprintf(outfile, ", FPGA_BITSTREAM_HF }");
|
||||||
|
else if (!memcmp("fpga_pm3_felica.ncd", version_string, sizeof("fpga_pm3_felica.ncd") - 1))
|
||||||
|
fprintf(outfile, ", FPGA_BITSTREAM_HF_FELICA }");
|
||||||
|
else
|
||||||
|
fprintf(outfile, ", FPGA_BITSTREAM_UNKNOWN }");
|
||||||
|
|
||||||
if (i != num_infiles - 1) {
|
if (i != num_infiles - 1) {
|
||||||
fprintf(outfile, ",");
|
fprintf(outfile, ",");
|
||||||
}
|
}
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue