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fixing the wrong calculations
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iceman1001
parent
5a56504fc1
commit
424e68dff6
3 changed files with 63 additions and 51 deletions
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@ -39,9 +39,14 @@
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* Current timing issues with ISO14443-b implementation
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* Proxmark3
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* Carrier Frequency 13.56MHz
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* 1 / 13 560 000 = 73.74 nano seconds ( 0.07374 µs )
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* SSP_CLK runs at 13.56MHz / 4 = 3,39MHz
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* 1 / 3 390 000 = 294.98 nano seconds ( 0.2949 µs )
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*
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*
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* 1 ETU = 9.4395 µs = 32 SSP_CLK = 128 FC
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* 1 SSP_CLK = 4 FC
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* 1 µs 3 SSP_CLK about 14 FC
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* PROBLEM 1.
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* ----------
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* one way of calculating time, that relates both to PM3 ssp_clk 3.39MHz, ISO freq of 13.56Mhz and ETUs
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@ -106,6 +111,9 @@
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*
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*/
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#ifndef MAX_14B_TIMEOUT
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// FWT(max) = 4949 ms or 4.95 seconds.
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// SSP_CLK = 4949000 * 3.39 = 16777120
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@ -122,8 +130,8 @@
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// ETU 14 * 9.4395 µS = 132 µS == 0.132ms
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// TR2, counting from start of PICC EOF 14 ETU.
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#define DELAY_ISO14443B_PICC_TO_PCD_READER ETU_TO_SSP(14)
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#define DELAY_ISO14443B_PCD_TO_PICC_READER ETU_TO_SSP(15)
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#define DELAY_ISO14443B_PICC_TO_PCD_READER HF14_ETU_TO_SSP(14)
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#define DELAY_ISO14443B_PCD_TO_PICC_READER HF14_ETU_TO_SSP(15)
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/* Guard Time (per 14443-2) in ETU
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*
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@ -138,41 +146,41 @@
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* TR0
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*/
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#ifndef ISO14B_TR0
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# define ISO14B_TR0 ETU_TO_SSP(32)
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# define ISO14B_TR0 HF14_ETU_TO_SSP(16)
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#endif
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#ifndef ISO14B_TR0_MAX
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# define ISO14B_TR0_MAX ETU_TO_SSP(32)
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# define ISO14B_TR0_MAX HF14_ETU_TO_SSP(32)
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// * TR0 - 32 ETU's maximum for ATQB only
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// * TR0 - FWT for all other commands
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// TR0 max is 151/fsc = 151/848kHz = 302us or 64 samples from FPGA
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// 32 ETU * 9.4395 µS == 302 µS
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// 32 * 8 = 256 sub carrier cycles,
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// 256 / 4 = 64 I/Q pairs.
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// TR0 max is 159 µS or 32 samples from FPGA
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// 16 ETU * 9.4395 µS == 151 µS
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// 16 * 8 = 128 sub carrier cycles,
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// 128 / 4 = 32 I/Q pairs.
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// since 1 I/Q pair after 4 subcarrier cycles at 848kHz subcarrier
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#endif
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// 8 ETU = 75 µS == 256 SSP_CLK
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#ifndef ISO14B_TR0_MIN
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# define ISO14B_TR0_MIN ETU_TO_SSP(8)
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# define ISO14B_TR0_MIN HF14_ETU_TO_SSP(8)
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#endif
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// Synchronization time (per 14443-2) in ETU
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// 10 ETU = 94,39 µS == 320 SSP_CLK
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// 16 ETU = 151 µS == 512 SSP_CLK
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#ifndef ISO14B_TR1_MIN
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# define ISO14B_TR1_MIN ETU_TO_SSP(10)
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# define ISO14B_TR1_MIN HF14_ETU_TO_SSP(16)
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#endif
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// Synchronization time (per 14443-2) in ETU
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// 25 ETU == 236 µS == 800 SSP_CLK
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#ifndef ISO14B_TR1_MAX
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# define ISO14B_TR1 ETU_TO_SSP(25)
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# define ISO14B_TR1 HF14_ETU_TO_SSP(25)
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#endif
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// Frame Delay Time PICC to PCD (per 14443-3 Amendment 1) in ETU
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// 14 ETU == 132 µS == 448 SSP_CLK
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#ifndef ISO14B_TR2
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# define ISO14B_TR2 ETU_TO_SSP(14)
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# define ISO14B_TR2 HF14_ETU_TO_SSP(14)
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#endif
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// 4sample
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@ -440,7 +448,7 @@ static void Uart14bInit(uint8_t *data) {
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// param timeout accepts ETU
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static void iso14b_set_timeout(uint32_t timeout_etu) {
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uint32_t ssp = ETU_TO_SSP(timeout_etu);
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uint32_t ssp = HF14_ETU_TO_SSP(timeout_etu);
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if (ssp > MAX_14B_TIMEOUT)
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ssp = MAX_14B_TIMEOUT;
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@ -1381,7 +1389,7 @@ static int Get14443bAnswerFromTag(uint8_t *response, uint16_t max_len, uint32_t
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}
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if (Demod.len > 0) {
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uint32_t sof_time = *eof_time - ETU_TO_SSP(
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uint32_t sof_time = *eof_time - HF14_ETU_TO_SSP(
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(Demod.len * (8 + 2)) // time for byte transfers
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// + (10) // time for TR1
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+ (10 + 2) // time for SOF transfer
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@ -1401,7 +1409,6 @@ static void TransmitFor14443b_AsReader(uint32_t *start_time) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SEND_SHALLOW_MOD);
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// TR2 minimum 14 ETUs
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if (*start_time < ISO14B_TR0) {
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// *start_time = DELAY_ARM_TO_TAG;
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@ -1544,7 +1551,7 @@ static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len, uint32_t
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// eof_time in ssp clocks, but bits was added here!
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// *eof_time = *start_time + (10 * ts->max) + 10 + 2 + 10;
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*eof_time = *start_time + ETU_TO_SSP(8 * ts->max);
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*eof_time = *start_time + HF14_ETU_TO_SSP(8 * ts->max);
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LogTrace(cmd, len, *start_time, *eof_time, NULL, true);
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}
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@ -1579,7 +1586,13 @@ int iso14443b_apdu(uint8_t const *msg, size_t msg_len, bool send_chaining, void
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CodeAndTransmit14443bAsReader(real_cmd, msg_len + 3, &start_time, &eof_time, true);
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eof_time += DELAY_ISO14443B_PCD_TO_PICC_READER;
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int len = Get14443bAnswerFromTag(rxdata, rxmaxlen, iso14b_timeout, &eof_time);
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// Activation frame waiting time
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// 65536/fc == 4833 µS
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// SSP_CLK = 4833 µS * 3.39 = 16384
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int len = Get14443bAnswerFromTag(rxdata, rxmaxlen, iso14b_timeout , &eof_time);
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FpgaDisableTracing();
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uint8_t *data_bytes = (uint8_t *) rxdata;
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@ -1836,7 +1849,7 @@ int iso14443b_select_xrx_card(iso14b_card_select_t *card) {
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int slot;
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for (slot = 0; slot < 4; slot++) {
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start_time = eof_time + ETU_TO_SSP(30); //(24); // next slot after 24 ETU
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start_time = eof_time + HF14_ETU_TO_SSP(30); //(24); // next slot after 24 ETU
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retlen = Get14443bAnswerFromTag(x_atqb, sizeof(x_atqb), iso14b_timeout, &eof_time);
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