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Add hw tia to trigger a new Timing Interval Acquisition

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This commit is contained in:
Philippe Teuwen 2019-10-15 14:21:26 +02:00
commit 3fce47d023
8 changed files with 109 additions and 39 deletions
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1
bootrom/Makefile
View file

@ -9,6 +9,7 @@
# DO NOT use thumb mode in the phase 1 bootloader since that generates a section with glue code
ARMSRC =
THUMBSRC = usb_cdc.c \
clocks.c \
bootrom.c
ASMSRC = ram-reset.s flash-reset.s

41
bootrom/bootrom.c
View file

@ -6,6 +6,7 @@
// Main code for the bootloader
//-----------------------------------------------------------------------------
#include "clocks.h"
#include "usb_cdc.h"
#include "proxmark3_arm.h"
@ -68,45 +69,7 @@ static void ConfigClocks(void) {
(1 << AT91C_ID_PWMC) |
(1 << AT91C_ID_UDP);
// worst case scenario, with MAINCK = 16MHz xtal, startup delay is 1.4ms
// if SLCK slow clock runs at its worst case (max) frequency of 42kHz
// max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
// enable main oscillator and set startup delay
AT91C_BASE_PMC->PMC_MOR =
AT91C_CKGR_MOSCEN |
PMC_MAIN_OSC_STARTUP_DELAY(8);
// wait for main oscillator to stabilize
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) {};
// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
// PLL output is MAINCK * multiplier / divisor = 16MHz * 12 / 2 = 96MHz
AT91C_BASE_PMC->PMC_PLLR =
PMC_PLL_DIVISOR(2) |
//PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
PMC_PLL_COUNT_BEFORE_LOCK(0x3F) |
PMC_PLL_FREQUENCY_RANGE(0) |
PMC_PLL_MULTIPLIER(12) |
PMC_PLL_USB_DIVISOR(1);
// wait for PLL to lock
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) {};
// we want a master clock (MCK) to be PLL clock / 2 = 96MHz / 2 = 48MHz
// datasheet recommends that this register is programmed in two operations
// when changing to PLL, program the prescaler first then the source
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
// wait for main clock ready signal
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) {};
// set the source to PLL
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
// wait for main clock ready signal
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) {};
mck_from_slck_to_pll(true);
}
static void Fatal(void) {