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CHG: @ikarus23 removed all missleadning warnings for GCC6.1.1.

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This commit is contained in:
iceman1001 2016-09-26 21:38:19 +02:00
commit 3c6542087e
3 changed files with 16 additions and 21 deletions
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15
bootrom/bootrom.c
View file

@ -49,8 +49,7 @@ static void ConfigClocks(void)
PMC_MAIN_OSC_STARTUP_DELAY(8); PMC_MAIN_OSC_STARTUP_DELAY(8);
// wait for main oscillator to stabilize // wait for main oscillator to stabilize
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) ) while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) ) {};
;
// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00 // PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10 // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
@ -63,8 +62,7 @@ static void ConfigClocks(void)
PMC_PLL_USB_DIVISOR(1); PMC_PLL_USB_DIVISOR(1);
// wait for PLL to lock // wait for PLL to lock
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ) while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ) {};
;
// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
// datasheet recommends that this register is programmed in two operations // datasheet recommends that this register is programmed in two operations
@ -72,15 +70,13 @@ static void ConfigClocks(void)
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
// wait for main clock ready signal // wait for main clock ready signal
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
;
// set the source to PLL // set the source to PLL
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK; AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
// wait for main clock ready signal // wait for main clock ready signal
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
;
} }
static void Fatal(void) { static void Fatal(void) {
@ -199,8 +195,7 @@ static void flash_mode(int externally_entered)
size_t rx_len; size_t rx_len;
usb_enable(); usb_enable();
for (volatile size_t i=0; i<0x100000; i++) for (volatile size_t i=0; i<0x100000; i++) {};
;
for(;;) { for(;;) {
WDT_HIT(); WDT_HIT();

9
client/cmdhf14a.c
View file

@ -655,14 +655,17 @@ int CmdHF14ACmdRaw(const char *cmd) {
c.arg[2] = 13560000 / 1000 / (8*16) * timeout; // timeout in ETUs (time to transfer 1 bit, approx. 9.4 us) c.arg[2] = 13560000 / 1000 / (8*16) * timeout; // timeout in ETUs (time to transfer 1 bit, approx. 9.4 us)
} }
if(power) if(power) {
c.arg[0] |= ISO14A_NO_DISCONNECT; c.arg[0] |= ISO14A_NO_DISCONNECT;
}
if(datalen>0) if(datalen>0) {
c.arg[0] |= ISO14A_RAW; c.arg[0] |= ISO14A_RAW;
}
if(topazmode) if(topazmode) {
c.arg[0] |= ISO14A_TOPAZMODE; c.arg[0] |= ISO14A_TOPAZMODE;
}
// Max buffer is USB_CMD_DATA_SIZE // Max buffer is USB_CMD_DATA_SIZE
datalen = (datalen > USB_CMD_DATA_SIZE) ? USB_CMD_DATA_SIZE : datalen; datalen = (datalen > USB_CMD_DATA_SIZE) ? USB_CMD_DATA_SIZE : datalen;

9
common/lfdemod.c
View file

@ -81,12 +81,9 @@ size_t removeParity(uint8_t *BitStream, size_t startIdx, uint8_t pLen, uint8_t p
j--; // overwrite parity with next data j--; // overwrite parity with next data
// if parity fails then return 0 // if parity fails then return 0
switch (pType) { switch (pType) {
case 3: if (BitStream[j]==1) return 0; break; //should be 0 spacer bit case 3: if (BitStream[j]==1) { return 0 }; break; //should be 0 spacer bit
case 2: if (BitStream[j]==0) return 0; break; //should be 1 spacer bit case 2: if (BitStream[j]==0) { return 0 }; break; //should be 1 spacer bit
default: //test parity default: if (parityTest(parityWd, pLen, pType) == 0) { return 0; } break; //test parity
if (parityTest(parityWd, pLen, pType) == 0)
return 0;
break;
} }
bitCnt+=(pLen-1); bitCnt+=(pLen-1);
parityWd = 0; parityWd = 0;