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iso15 sniffing: intragrate 2SC sniffing in same FPGA mode
switching Fpgamode while sniffing with FpgaWriteConfWord() was sometimes too long so the tag answer start was lost. Now, (only with FPGA_BITSTREAM_HF_15) with "FPGA_HF_READER_MODE_SNIFF_AMPLITUDE | FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ": the amplitude is shrank from its 2 LSB bits and those 2 bits are now used to return the current frequency. From my tests, this 2 bits reduction does not affect quality of 1SC sniffing, but it may have slightly reduced the receiving range. FPGA FSK decoding code is also improved.
This commit is contained in:
Yann GASCUEL
parent
1f7bce5580
commit
38d49097f9
7 changed files with 469 additions and 52 deletions
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@ -162,7 +162,9 @@ void FpgaSetupSsc(uint16_t fpga_mode) {
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// 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync
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// pulse, no output sync
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if ((fpga_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_READER && (FpgaGetCurrent() == FPGA_BITSTREAM_HF || FpgaGetCurrent() == FPGA_BITSTREAM_HF_15)) {
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if (((fpga_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_READER ||
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(fpga_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_FSK_READER) &&
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(FpgaGetCurrent() == FPGA_BITSTREAM_HF || FpgaGetCurrent() == FPGA_BITSTREAM_HF_15)) {
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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} else {
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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@ -106,14 +106,7 @@ thres| x x x x x x x x
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#define FPGA_HF_READER_SUBCARRIER_848_KHZ (0<<4)
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#define FPGA_HF_READER_SUBCARRIER_424_KHZ (1<<4)
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#define FPGA_HF_READER_SUBCARRIER_212_KHZ (2<<4)
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#define FPGA_HF_FSK_READER_OUTPUT_1695_KHZ (0<<0)
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#define FPGA_HF_FSK_READER_OUTPUT_848_KHZ (1<<0)
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#define FPGA_HF_FSK_READER_OUTPUT_424_KHZ (2<<0)
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#define FPGA_HF_FSK_READER_OUTPUT_212_KHZ (3<<0)
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#define FPGA_HF_FSK_READER_NOPOWER (0<<4)
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#define FPGA_HF_FSK_READER_WITHPOWER (1<<4)
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#define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ (3<<4)
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// Options for the HF simulated tag, how to modulate
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#define FPGA_HF_SIMULATOR_NO_MODULATION 0x0 // 0000
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@ -1269,10 +1269,10 @@ void AcquireRawAdcSamplesIso15693(void) {
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// Returns: true if we received a EOF
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// false if we are still waiting for some more
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//=============================================================================
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#define DEBUG 0
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#define FREQ_IS_484(f) (f >= 26 && f <= 30)
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#define FREQ_IS_424(f) (f >= 30 && f <= 34)
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#define FREQ_IS_0(f) (f <= 24 || f >= 36)
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//#define DEBUG 1
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#define FREQ_IS_484(f) ((f & 1) == 1) //(f >= 26 && f <= 30)
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#define FREQ_IS_424(f) ((f & 2) == 2) //(f >= 30 && f <= 34)
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#define FREQ_IS_0(f) ((f & 3) == 0) // (f <= 24 || f >= 36)
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#define SEOF_COUNT(c, s) ((s) ? (c >= 11 && c <= 13) : (c >= 44 && c <= 52))
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#define LOGIC_COUNT(c, s) ((s) ? (c >= 3 && c <= 6) : (c >= 13 && c <= 21))
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#define MAX_COUNT(c, s) ((s) ? (c >= 13) : (c >= 52))
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@ -1320,7 +1320,7 @@ static void DecodeTagFSKInit(DecodeTagFSK_t *DecodeTag, uint8_t *data, uint16_t
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// Performances of this function are crutial for stability
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// as it is called in real time for every samples
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static int inline __attribute__((always_inline)) Handle15693FSKSamplesFromTag(uint8_t freq, DecodeTagFSK_t *DecodeTag, bool recv_speed)
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static int RAMFUNC Handle15693FSKSamplesFromTag(uint8_t freq, DecodeTagFSK_t *DecodeTag, bool recv_speed, int samples)
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{
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switch(DecodeTag->state) {
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case STATE_FSK_BEFORE_SOF:
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@ -1546,7 +1546,7 @@ void SniffIso15693(uint8_t jam_search_len, uint8_t *jam_search_string) {
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uint8_t cmd[ISO15693_MAX_COMMAND_LENGTH] = {0};
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DecodeReaderInit(&dreader, cmd, sizeof(cmd), jam_search_len, jam_search_string);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SNIFF_AMPLITUDE);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SNIFF_AMPLITUDE | FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ);
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LED_D_OFF();
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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@ -1639,10 +1639,6 @@ void SniffIso15693(uint8_t jam_search_len, uint8_t *jam_search_string) {
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DecodeTagFSKReset(&dtagfsk);
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reader_is_active = false;
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expect_tag_answer = true;
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if (expect_fsk_answer)
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{
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_FSK_READER | FPGA_HF_FSK_READER_OUTPUT_212_KHZ | FPGA_HF_FSK_READER_NOPOWER);
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}
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} else if (Handle15693SampleFromReader(sniffdata & 0x01, &dreader)) {
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uint32_t eof_time = dma_start_time + (samples * 16) + 16 - DELAY_READER_TO_ARM_SNIFF; // end of EOF
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@ -1662,11 +1658,6 @@ void SniffIso15693(uint8_t jam_search_len, uint8_t *jam_search_string) {
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DecodeTagFSKReset(&dtagfsk);
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reader_is_active = false;
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expect_tag_answer = true;
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if (expect_fsk_answer)
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{
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_FSK_READER | FPGA_HF_FSK_READER_OUTPUT_212_KHZ | FPGA_HF_FSK_READER_NOPOWER);
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}
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} else {
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reader_is_active = (dreader.state >= STATE_READER_RECEIVE_DATA_1_OUT_OF_4);
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}
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@ -1676,7 +1667,7 @@ void SniffIso15693(uint8_t jam_search_len, uint8_t *jam_search_string) {
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if (!expect_fsk_answer)
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{
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if (Handle15693SamplesFromTag(sniffdata >> 2, &dtag)) {
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if (Handle15693SamplesFromTag((sniffdata >> 4) << 2, &dtag)) {
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uint32_t eof_time = dma_start_time + (samples * 16) - DELAY_TAG_TO_ARM_SNIFF; // end of EOF
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if (dtag.lastBit == SOF_PART2) {
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@ -1700,7 +1691,7 @@ void SniffIso15693(uint8_t jam_search_len, uint8_t *jam_search_string) {
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}
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else
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{
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if (Handle15693FSKSamplesFromTag(sniffdata >> 8, &dtagfsk, expect_fast_answer)) {
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if (Handle15693FSKSamplesFromTag((sniffdata >> 2) & 0x3, &dtagfsk, expect_fast_answer, samples-fsksamples)) {
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uint32_t eof_time = dma_start_time + (samples * 16) - DELAY_TAG_TO_ARM_SNIFF; // end of EOF
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if (dtagfsk.lastBit == SOF) {
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eof_time -= (8 * 16); // needed 8 additional samples to confirm single SOF (iCLASS)
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@ -1719,7 +1710,6 @@ void SniffIso15693(uint8_t jam_search_len, uint8_t *jam_search_string) {
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tag_is_active = false;
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expect_fsk_answer = false;
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SNIFF_AMPLITUDE);
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}
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else if (Handle15693FSKSamplesFromTag(sniffdata & 0xFF, &dtagfsk, expect_fast_answer)) {
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@ -1741,7 +1731,6 @@ void SniffIso15693(uint8_t jam_search_len, uint8_t *jam_search_string) {
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tag_is_active = false;
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expect_fsk_answer = false;
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SNIFF_AMPLITUDE);
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} else {
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tag_is_active = (dtagfsk.state >= STATE_FSK_RECEIVING_DATA_484);
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}
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@ -22,7 +22,7 @@ fpga_felica.ngc: fpga_felica.v fpga.ucf xst_felica.scr util.v hi_simulate.v hi_r
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$(info [-] XST $@)
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$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_felica.scr
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fpga_hf_15.ngc: fpga_hf_15.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_reader.v hi_iso14443a.v hi_sniffer.v hi_get_trace.v hi_read_fsk.v
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fpga_hf_15.ngc: fpga_hf_15.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_reader_15.v hi_iso14443a.v hi_sniffer.v hi_get_trace.v
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$(Q)$(RM) $@
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$(info [-] XST $@)
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$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_hf_15.scr
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Binary file not shown.
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@ -46,6 +46,7 @@
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`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
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`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
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`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
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`define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ 3
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`define FPGA_HF_FSK_READER_OUTPUT_1695_KHZ 0
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`define FPGA_HF_FSK_READER_OUTPUT_848_KHZ 1
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@ -74,14 +75,13 @@
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`define FPGA_HF_ISO18092_FLAG_424K 2 // 0010 should enable 414k mode (untested). No autodetect
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`define FPGA_HF_ISO18092_FLAG_READER 4 // 0100 enables antenna power, to act as a reader instead of tag
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`include "hi_reader.v"
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`include "hi_reader_15.v"
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`include "hi_simulate.v"
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//`include "hi_iso14443a.v"
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`include "hi_sniffer.v"
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`include "util.v"
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// `include "hi_flite.v"
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`include "hi_get_trace.v"
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`include "hi_read_fsk.v"
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module fpga_hf_15(
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input spck, output miso, input mosi, input ncs,
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@ -221,15 +221,6 @@ hi_get_trace gt(
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gt_ssp_frame, gt_ssp_din, gt_ssp_clk
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);
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// 110 - HF Read FSK
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hi_read_fsk hrf(
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ck_1356meg,
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hrf_pwr_lo, hrf_pwr_hi, hrf_pwr_oe1, hrf_pwr_oe2, hrf_pwr_oe3, hrf_pwr_oe4,
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adc_d, hrf_adc_clk,
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hrf_ssp_frame, hrf_ssp_din, hrf_ssp_clk,
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subcarrier_frequency, minor_mode
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);
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// Major modes:
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// 000 -- HF reader; subcarrier frequency and modulation depth selectable
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// 001 -- HF simulated tag
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@ -237,21 +228,20 @@ hi_read_fsk hrf(
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// 011 -- HF sniff
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// 100 -- HF ISO18092 FeliCa
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// 101 -- HF get trace
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// 110 -- HF Read FSK
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// 110 -- unused
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// 111 -- FPGA_MAJOR_MODE_OFF
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// 000 001 010 011 100 101 110 111
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mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, 1'b0, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, hrf_ssp_clk, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, 1'b0, he_ssp_din, hfl_ssp_din, gt_ssp_din, hrf_ssp_din, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, 1'b0, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, hrf_ssp_frame, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, 1'b0, he_pwr_oe1, hfl_pwr_oe1, 1'b0, hrf_pwr_oe1, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, 1'b0, he_pwr_oe2, hfl_pwr_oe2, 1'b0, hrf_pwr_oe2, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, 1'b0, he_pwr_oe3, hfl_pwr_oe3, 1'b0, hrf_pwr_oe3, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, 1'b0, he_pwr_oe4, hfl_pwr_oe4, 1'b0, hrf_pwr_oe4, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, 1'b0, he_pwr_lo, hfl_pwr_lo, 1'b0, hrf_pwr_lo, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, 1'b0, he_pwr_hi, hfl_pwr_hi, 1'b0, hrf_pwr_hi, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, 1'b0, he_adc_clk, hfl_adc_clk, 1'b0, hrf_adc_clk, 1'b0);
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mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, 1'b0, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, 1'b0, he_ssp_din, hfl_ssp_din, gt_ssp_din, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, 1'b0, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, 1'b0, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, 1'b0, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, 1'b0, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, 1'b0, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, 1'b0, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, 1'b0, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, 1'b0, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, 1'b0, he_dbg, hfl_dbg, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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443
fpga-xc2s30/hi_reader_15.v
Normal file
443
fpga-xc2s30/hi_reader_15.v
Normal file
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@ -0,0 +1,443 @@
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//-----------------------------------------------------------------------------
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//
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// copied from hi_reader.v by Jonathan Westhues, April 2006
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// modified to add support for iso15 2sc mode by lnv42, Feb 2022
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//-----------------------------------------------------------------------------
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module hi_reader(
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ck_1356meg,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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dbg,
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subcarrier_frequency, minor_mode
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);
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input ck_1356meg;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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output dbg;
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input [1:0] subcarrier_frequency;
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input [3:0] minor_mode;
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assign adc_clk = ck_1356meg; // sample frequency is 13,56 MHz
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// When we're a reader, we just need to do the BPSK demod; but when we're an
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// eavesdropper, we also need to pick out the commands sent by the reader,
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// using AM. Do this the same way that we do it for the simulated tag.
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reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
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reg [11:0] has_been_low_for;
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always @(negedge adc_clk)
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begin
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if (& adc_d[7:0]) after_hysteresis <= 1'b1;
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else if (~(| adc_d[7:0])) after_hysteresis <= 1'b0;
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if (after_hysteresis)
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begin
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has_been_low_for <= 12'd0;
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end
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else
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begin
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if (has_been_low_for == 12'd4095)
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begin
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has_been_low_for <= 12'd0;
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after_hysteresis <= 1'b1;
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end
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else
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has_been_low_for <= has_been_low_for + 1;
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end
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end
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// Let us report a correlation every 64 samples. I.e.
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// one Q/I pair after 4 subcarrier cycles for the 848kHz subcarrier,
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// one Q/I pair after 2 subcarrier cycles for the 424kHz subcarriers,
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// one Q/I pair for each subcarrier cyle for the 212kHz subcarrier.
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// We need a 6-bit counter for the timing.
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reg [5:0] corr_i_cnt;
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always @(negedge adc_clk)
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begin
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corr_i_cnt <= corr_i_cnt + 1;
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end
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reg [1:0] fskout = 2'd0;
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reg last0 = 1'b0;
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||||
|
||||
reg [7:0] avg = 8'd0;
|
||||
reg [127:0] avg128 = 128'd0;
|
||||
reg [7:0] diff16 = 8'd0;
|
||||
reg [7:0] diff28 = 8'd0;
|
||||
reg [7:0] diff32 = 8'd0;
|
||||
|
||||
reg [11:0] match16 = 12'd0;
|
||||
reg [11:0] match32 = 12'd0;
|
||||
reg [11:0] match28 = 12'd0;
|
||||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (corr_i_cnt[0] == 1'b0) // every 2 clock
|
||||
begin
|
||||
avg = adc_d[7:1];
|
||||
end
|
||||
else
|
||||
begin
|
||||
avg = avg + adc_d[7:1];
|
||||
if (corr_i_cnt[0] == 1'b1) // every 2 clock
|
||||
begin
|
||||
if (avg > avg128[63:56])
|
||||
diff16 = avg - avg128[63:56];
|
||||
else
|
||||
diff16 = avg128[63:56] - avg;
|
||||
|
||||
if (avg > avg128[111:104])
|
||||
diff28 = avg - avg128[111:104];
|
||||
else
|
||||
diff28 = avg128[111:104] - avg;
|
||||
|
||||
if (avg > avg128[127:120])
|
||||
diff32 = avg - avg128[127:120];
|
||||
else
|
||||
diff32 = avg128[127:120] - avg;
|
||||
|
||||
avg128[127:8] = avg128[119:0];
|
||||
avg128[7:0] = avg;
|
||||
|
||||
|
||||
if (corr_i_cnt[4:1] == 4'b0000) // every 32 clock (8*4)
|
||||
begin
|
||||
match16 = diff16;
|
||||
match28 = diff28;
|
||||
match32 = diff32;
|
||||
end
|
||||
else
|
||||
begin
|
||||
match16 = match16 + diff16;
|
||||
match28 = match28 + diff28;
|
||||
match32 = match32 + diff32;
|
||||
|
||||
if (corr_i_cnt[4:1] == 4'b1111) // every 32 clock (8*4)
|
||||
begin
|
||||
last0 = (fskout == 2'b0);
|
||||
if (match16 < 12'd64 && last0)
|
||||
fskout = 2'b00; // not yet started
|
||||
else if ((match16 | match28 | match32) == 12'b0)
|
||||
fskout = 2'b00; // signal likely ended
|
||||
else if (((match16 <= match28 + 12'd16) && (match16 <= match32+ 12'd16)) ||
|
||||
(match28 <= 12'd16 && match32 <= 12'd16))
|
||||
begin
|
||||
if (!last0)
|
||||
fskout = 2'b11; // 16 match better than 28 or 32 but already started
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (match28 < match32)
|
||||
begin
|
||||
diff28 = match32 - match28;
|
||||
diff16 = match16 - match28;
|
||||
if (diff28*2 > diff16)
|
||||
fskout = 2'b01;
|
||||
else if (!last0)
|
||||
begin
|
||||
fskout = 2'b01;
|
||||
end
|
||||
end
|
||||
else //if (match32 <= match28)
|
||||
begin
|
||||
diff32 = match28 - match32;
|
||||
diff16 = match16 - match32;
|
||||
if (diff32*2 > diff16)
|
||||
fskout = 2'b10;
|
||||
else if (!last0)
|
||||
begin
|
||||
fskout = 2'b10;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// A couple of registers in which to accumulate the correlations. From the 64 samples
|
||||
// we would add at most 32 times the difference between unmodulated and modulated signal. It should
|
||||
// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
|
||||
// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
|
||||
// Temporary we might need more bits. For the 212kHz subcarrier we could possible add 32 times the
|
||||
// maximum signal value before a first subtraction would occur. 32 * 255 = 8160 can be held in 13 bits.
|
||||
// Add one bit for sign -> need 14 bit registers but final result will fit into 12 bits.
|
||||
reg signed [13:0] corr_i_accum;
|
||||
reg signed [13:0] corr_q_accum;
|
||||
// we will report maximum 8 significant bits
|
||||
reg signed [7:0] corr_i_out;
|
||||
reg signed [7:0] corr_q_out;
|
||||
|
||||
|
||||
// the amplitude of the subcarrier is sqrt(ci^2 + cq^2).
|
||||
// approximate by amplitude = max(|ci|,|cq|) + 1/2*min(|ci|,|cq|)
|
||||
reg [13:0] corr_amplitude, abs_ci, abs_cq, max_ci_cq;
|
||||
reg [12:0] min_ci_cq_2; // min_ci_cq / 2
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (corr_i_accum[13] == 1'b0)
|
||||
abs_ci <= corr_i_accum;
|
||||
else
|
||||
abs_ci <= -corr_i_accum;
|
||||
|
||||
if (corr_q_accum[13] == 1'b0)
|
||||
abs_cq <= corr_q_accum;
|
||||
else
|
||||
abs_cq <= -corr_q_accum;
|
||||
|
||||
if (abs_ci > abs_cq)
|
||||
begin
|
||||
max_ci_cq <= abs_ci;
|
||||
min_ci_cq_2 <= abs_cq / 2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
max_ci_cq <= abs_cq;
|
||||
min_ci_cq_2 <= abs_ci / 2;
|
||||
end
|
||||
|
||||
corr_amplitude <= max_ci_cq + min_ci_cq_2;
|
||||
|
||||
end
|
||||
|
||||
|
||||
// The subcarrier reference signals
|
||||
reg subcarrier_I;
|
||||
reg subcarrier_Q;
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
|
||||
begin
|
||||
subcarrier_I = ~corr_i_cnt[3];
|
||||
subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
|
||||
end
|
||||
else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
|
||||
begin
|
||||
subcarrier_I = ~corr_i_cnt[5];
|
||||
subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
|
||||
end
|
||||
else
|
||||
begin // 424 kHz
|
||||
subcarrier_I = ~corr_i_cnt[4];
|
||||
subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ADC data appears on the rising edge, so sample it on the falling edge
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
// These are the correlators: we correlate against in-phase and quadrature
|
||||
// versions of our reference signal, and keep the (signed) results or the
|
||||
// resulting amplitude to send out later over the SSP.
|
||||
if (corr_i_cnt == 6'd0)
|
||||
begin
|
||||
if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE)
|
||||
begin
|
||||
if (subcarrier_frequency == `FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ)
|
||||
begin
|
||||
// send amplitude + 2 bits fsk (2sc) signal + 2 bits reader signal
|
||||
corr_i_out <= corr_amplitude[13:6];
|
||||
corr_q_out <= {corr_amplitude[5:2], fskout, after_hysteresis_prev_prev, after_hysteresis_prev};
|
||||
end
|
||||
else
|
||||
begin
|
||||
// send amplitude plus 2 bits reader signal
|
||||
corr_i_out <= corr_amplitude[13:6];
|
||||
corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
|
||||
end
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
|
||||
begin
|
||||
// Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
|
||||
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
|
||||
corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
|
||||
else // truncate to maximum value
|
||||
if (corr_i_accum[13] == 1'b0)
|
||||
corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
|
||||
else
|
||||
corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
|
||||
|
||||
// Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
|
||||
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
|
||||
corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
|
||||
else // truncate to maximum value
|
||||
if (corr_q_accum[13] == 1'b0)
|
||||
corr_q_out <= {7'b0111111, after_hysteresis_prev};
|
||||
else
|
||||
corr_q_out <= {7'b1000000, after_hysteresis_prev};
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE)
|
||||
begin
|
||||
// send amplitude
|
||||
corr_i_out <= {2'b00, corr_amplitude[13:8]};
|
||||
corr_q_out <= corr_amplitude[7:0];
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
|
||||
begin
|
||||
// Send 8 bits of in phase tag signal
|
||||
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
|
||||
corr_i_out <= corr_i_accum[11:4];
|
||||
else // truncate to maximum value
|
||||
if (corr_i_accum[13] == 1'b0)
|
||||
corr_i_out <= 8'b01111111;
|
||||
else
|
||||
corr_i_out <= 8'b10000000;
|
||||
|
||||
// Send 8 bits of quadrature phase tag signal
|
||||
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
|
||||
corr_q_out <= corr_q_accum[11:4];
|
||||
else // truncate to maximum value
|
||||
if (corr_q_accum[13] == 1'b0)
|
||||
corr_q_out <= 8'b01111111;
|
||||
else
|
||||
corr_q_out <= 8'b10000000;
|
||||
end
|
||||
|
||||
// for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
|
||||
after_hysteresis_prev_prev <= after_hysteresis;
|
||||
|
||||
// Initialize next correlation.
|
||||
// Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate.
|
||||
corr_i_accum <= $signed({1'b0, adc_d});
|
||||
corr_q_accum <= $signed({1'b0, adc_d});
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (subcarrier_I)
|
||||
corr_i_accum <= corr_i_accum + $signed({1'b0, adc_d});
|
||||
else
|
||||
corr_i_accum <= corr_i_accum - $signed({1'b0, adc_d});
|
||||
|
||||
if (subcarrier_Q)
|
||||
corr_q_accum <= corr_q_accum + $signed({1'b0, adc_d});
|
||||
else
|
||||
corr_q_accum <= corr_q_accum - $signed({1'b0, adc_d});
|
||||
end
|
||||
|
||||
// for each Q/I pair report two reader signal samples when sniffing. Store the 2nd.
|
||||
if (corr_i_cnt == 6'd32)
|
||||
after_hysteresis_prev <= after_hysteresis;
|
||||
|
||||
// Then the result from last time is serialized and send out to the ARM.
|
||||
// We get one report each cycle, and each report is 16 bits, so the
|
||||
// ssp_clk should be the adc_clk divided by 64/16 = 4.
|
||||
// ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
|
||||
|
||||
if (corr_i_cnt[1:0] == 2'b00)
|
||||
begin
|
||||
// Don't shift if we just loaded new data, obviously.
|
||||
if (corr_i_cnt != 6'd0)
|
||||
begin
|
||||
corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
|
||||
corr_q_out[7:1] <= corr_q_out[6:0];
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// ssp clock and frame signal for communication to and from ARM
|
||||
// _____ _____ _____ _
|
||||
// ssp_clk | |_____| |_____| |_____|
|
||||
// _____
|
||||
// ssp_frame ___| |____________________________
|
||||
// ___________ ___________ ___________ _
|
||||
// ssp_d_in X___________X___________X___________X_
|
||||
//
|
||||
// corr_i_cnt 0 1 2 3 4 5 6 7 8 9 10 11 12 ...
|
||||
//
|
||||
|
||||
reg ssp_clk;
|
||||
reg ssp_frame;
|
||||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (corr_i_cnt[1:0] == 2'b00)
|
||||
ssp_clk <= 1'b1;
|
||||
|
||||
if (corr_i_cnt[1:0] == 2'b10)
|
||||
ssp_clk <= 1'b0;
|
||||
|
||||
// set ssp_frame signal for corr_i_cnt = 1..3
|
||||
// (send one frame with 16 Bits)
|
||||
if (corr_i_cnt == 6'd1)
|
||||
ssp_frame <= 1'b1;
|
||||
|
||||
if (corr_i_cnt == 6'd3)
|
||||
ssp_frame <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
assign ssp_din = corr_i_out[7];
|
||||
|
||||
|
||||
// a jamming signal
|
||||
reg jam_signal;
|
||||
reg [3:0] jam_counter;
|
||||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (corr_i_cnt == 6'd0)
|
||||
begin
|
||||
jam_counter <= jam_counter + 1;
|
||||
jam_signal <= jam_counter[1] ^ jam_counter[3];
|
||||
end
|
||||
end
|
||||
|
||||
// Antenna drivers
|
||||
reg pwr_hi, pwr_oe4;
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (minor_mode == `FPGA_HF_READER_MODE_SEND_SHALLOW_MOD)
|
||||
begin
|
||||
pwr_hi = ck_1356meg;
|
||||
pwr_oe4 = ssp_dout;
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_SEND_FULL_MOD)
|
||||
begin
|
||||
pwr_hi = ck_1356meg & ~ssp_dout;
|
||||
pwr_oe4 = 1'b0;
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_SEND_JAM)
|
||||
begin
|
||||
pwr_hi = ck_1356meg & jam_signal;
|
||||
pwr_oe4 = 1'b0;
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ
|
||||
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE
|
||||
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE)
|
||||
begin // all off
|
||||
pwr_hi = 1'b0;
|
||||
pwr_oe4 = 1'b0;
|
||||
end
|
||||
else // receiving from tag
|
||||
begin
|
||||
pwr_hi = ck_1356meg;
|
||||
pwr_oe4 = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// always on
|
||||
assign pwr_oe1 = 1'b0;
|
||||
assign pwr_oe3 = 1'b0;
|
||||
|
||||
// Unused.
|
||||
assign pwr_lo = 1'b0;
|
||||
assign pwr_oe2 = 1'b0;
|
||||
|
||||
// Debug Output
|
||||
assign dbg = corr_i_cnt[3];
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue