mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-14 18:48:13 -07:00
Second Pass rewrite of flashmem. added command 'mem spibaud' to switch between 24/48Mhz operation. All is more consistant, less messy. All logic rewrittent avoiding multiple flashinit/flashstop. busywait is now at it's lowest possible. Beware : 48Mhz is VERY buggy cause of sillicon bug (see source for more info), and doesn't give much more than 24Mhz for now since we doubled nearly every operation speed here.
This commit is contained in:
Colin J. Brigato
parent
76e2d7502a
commit
368fe11df0
5 changed files with 201 additions and 189 deletions
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@ -1,11 +1,6 @@
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#include "flashmem.h"
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#define MCK 48000000
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//#define FLASH_BAUD 24000000
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//define FLASH_BAUD 33000000
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#define FLASH_BAUD MCK/2
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#define FLASH_FASTBAUD MCK
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/* here: use NCPS2 @ PA10: */
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#define SPI_CSR_NUM 2
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@ -18,10 +13,17 @@
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#define SPI_DLYBCT(delay, masterClock) ((uint32_t) ((((masterClock) / 1000000) * (delay)) / 32000) << 24)
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uint32_t FLASHMEM_SPIBAUDRATE = FLASH_BAUD;
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void FlashmemSetSpiBaudrate(uint32_t baudrate){
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FLASHMEM_SPIBAUDRATE = baudrate;
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Dbprintf("Spi Baudrate : %dMhz", FLASHMEM_SPIBAUDRATE/1000000);
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}
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// initialize
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bool FlashInit(bool fast) {
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FlashSetup(fast);
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bool FlashInit() {
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FlashSetup(FLASHMEM_SPIBAUDRATE);
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StartTicks();
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@ -33,7 +35,7 @@ bool FlashInit(bool fast) {
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return true;
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}
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void FlashSetup(bool fast){
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void FlashSetup(uint32_t baudrate){
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//WDT_DISABLE
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AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
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@ -79,13 +81,12 @@ void FlashSetup(bool fast){
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AT91C_SPI_PS_FIXED | // Fixed Peripheral Select
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AT91C_SPI_MSTR; // Master Mode
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int baudrate = FLASH_BAUD;
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uint8_t csaat = 1;
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int dlybct = 0;
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if (fast) {
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uint32_t dlybct = 0;
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if (baudrate > FLASH_MINFAST) {
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baudrate = FLASH_FASTBAUD;
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//csaat = 0;
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dlybct = MCK/32;
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dlybct = 1500;
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}
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AT91C_BASE_SPI->SPI_CSR[2] =
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@ -100,28 +101,28 @@ void FlashSetup(bool fast){
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// transferred in the shifter. This can imply for example, that the second data is sent twice.
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// COLIN :: For now we STILL use CSAAT=1 to avoid having to (de)assert NPCS manually via PIO lines and we deal with delay
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( csaat << 3) |
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/* Spi modes:
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Mode CPOL CPHA NCPHA
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0 0 0 1 clock normally low read on rising edge
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1 0 1 0 clock normally low read on falling edge
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2 1 0 1 clock normally high read on falling edge
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3 1 1 0 clock normally high read on rising edge
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However, page 512 of the AT91SAM7Sx datasheet say "Note that in SPI
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master mode the ATSAM7S512/256/128/64/321/32 does not sample the data
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(MISO) on the opposite edge where data clocks out (MOSI) but the same
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edge is used as shown in Figure 36-3 and Figure 36-4." Figure 36-3
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shows that CPOL=NCPHA=0 or CPOL=NCPHA=1 samples on the rising edge and
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that the data changes sometime after the rising edge (about 2 ns). To
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be consistent with normal SPI operation, it is probably safe to say
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that the data changes on the falling edge and should be sampled on the
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rising edge. Therefore, it appears that NCPHA should be treated the
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same as CPHA. Thus:
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Mode CPOL CPHA NCPHA
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0 0 0 0 clock normally low read on rising edge
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1 0 1 1 clock normally low read on falling edge
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2 1 0 0 clock normally high read on falling edge
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3 1 1 1 clock normally high read on rising edge
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*/
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/* Spi modes:
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Mode CPOL CPHA NCPHA
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0 0 0 1 clock normally low read on rising edge
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1 0 1 0 clock normally low read on falling edge
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2 1 0 1 clock normally high read on falling edge
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3 1 1 0 clock normally high read on rising edge
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However, page 512 of the AT91SAM7Sx datasheet say "Note that in SPI
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master mode the ATSAM7S512/256/128/64/321/32 does not sample the data
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(MISO) on the opposite edge where data clocks out (MOSI) but the same
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edge is used as shown in Figure 36-3 and Figure 36-4." Figure 36-3
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shows that CPOL=NCPHA=0 or CPOL=NCPHA=1 samples on the rising edge and
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that the data changes sometime after the rising edge (about 2 ns). To
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be consistent with normal SPI operation, it is probably safe to say
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that the data changes on the falling edge and should be sampled on the
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rising edge. Therefore, it appears that NCPHA should be treated the
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same as CPHA. Thus:
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Mode CPOL CPHA NCPHA
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0 0 0 0 clock normally low read on rising edge
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1 0 1 1 clock normally low read on falling edge
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2 1 0 0 clock normally high read on falling edge
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3 1 1 1 clock normally high read on rising edge
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*/
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( 0 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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@ -161,10 +162,10 @@ uint16_t FlashSendByte(uint32_t data) {
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// send the data
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AT91C_BASE_SPI->SPI_TDR = data;
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while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TDRE) == 0){};
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//while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TDRE) == 0){};
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// wait recive transfer is complete
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while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RDRF) == 0);
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while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RDRF) == 0){};
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// reading incoming data
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return ((AT91C_BASE_SPI->SPI_RDR) & 0xFFFF);
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@ -187,6 +188,8 @@ bool Flash_CheckBusy(uint32_t timeout)
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StartCountUS();
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uint32_t _time = GetCountUS();
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if ( MF_DBGLEVEL > 3 ) Dbprintf("Checkbusy in...");
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do
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{
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if (!(Flash_ReadStat1() & BUSY))
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@ -249,37 +252,61 @@ void Flash_UniqueID(uint8_t *uid) {
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uint16_t Flash_ReadData(uint32_t address, uint8_t *out, uint16_t len) {
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if (!FlashInit(0)) return 0;
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if (!FlashInit()) return 0;
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// length should never be zero
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if (!len || Flash_CheckBusy(BUSY_TIMEOUT)) return 0;
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FlashSendByte(READDATA);
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FlashSendByte((address >> 16) & 0xFF);
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FlashSendByte((address >> 8) & 0xFF);
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FlashSendByte((address >> 0) & 0xFF);
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uint8_t cmd = READDATA;
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if(FASTFLASH) {
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cmd = FASTREAD;
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}
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FlashSendByte(cmd);
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Flash_TransferAdresse(address);
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if (FASTFLASH){
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FlashSendByte(DUMMYBYTE);
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}
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uint16_t i = 0;
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for (; i < (len - 1); i++)
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out[i] = FlashSendByte(0xFF);
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out[i] = FlashSendLastByte(0xFF);
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FlashStop();
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return len;
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}
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void Flash_TransferAdresse(uint32_t address){
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FlashSendByte((address >> 16) & 0xFF);
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FlashSendByte((address >> 8) & 0xFF);
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FlashSendByte((address >> 0) & 0xFF);
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}
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/* This ensure we can ReadData without having to cycle through initialization everytime */
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uint16_t Flash_ReadDataCont(uint32_t address, uint8_t *out, uint16_t len) {
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// length should never be zero
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if (!len) return 0;
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uint8_t cmd = READDATA;
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FlashSendByte(READDATA);
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FlashSendByte((address >> 16) & 0xFF);
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FlashSendByte((address >> 8) & 0xFF);
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FlashSendByte((address >> 0) & 0xFF);
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if(FASTFLASH) {
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cmd = FASTREAD;
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}
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FlashSendByte(cmd);
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Flash_TransferAdresse(address);
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if (FASTFLASH){
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FlashSendByte(DUMMYBYTE);
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}
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uint16_t i = 0;
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for (; i < (len - 1); i++)
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out[i] = FlashSendByte(0xFF);
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@ -289,32 +316,6 @@ uint16_t Flash_ReadDataCont(uint32_t address, uint8_t *out, uint16_t len) {
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return len;
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}
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uint16_t Flash_FastReadDataCont(uint32_t address, uint8_t *out, uint16_t len) {
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// length should never be zero
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if (!len) return 0;
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//if (Flash_CheckBusy(BUSY_TIMEOUT))
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//{return 0;}
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FlashSendByte(FASTREAD);
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FlashSendByte((address >> 16) & 0xFF);
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FlashSendByte((address >> 8) & 0xFF);
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FlashSendByte((address >> 0) & 0xFF);
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FlashSendByte(0xFF);
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//Flash_CheckBusy(BUSY_TIMEOUT);
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uint16_t i = 0;
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for (; i < (len - 1); i++)
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out[i] = FlashSendByte(0xFF);
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out[i] = FlashSendLastByte(0xFF);
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return len;
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}
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////////////////////////////////////////
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@ -338,13 +339,12 @@ uint16_t Flash_WriteData(uint32_t address, uint8_t *in, uint16_t len) {
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return 0;
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}
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if (!FlashInit(0)) {
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if (!FlashInit()) {
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if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
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return 0;
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}
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Flash_CheckBusy(BUSY_TIMEOUT);
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//Flash_ReadStat1();
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Flash_WriteEnable();
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@ -382,10 +382,8 @@ uint16_t Flash_WriteDataCont(uint32_t address, uint8_t *in, uint16_t len) {
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}
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//Flash_CheckBusy(100);
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//SpinDelay(1);
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Flash_CheckBusy(BUSY_TIMEOUT);
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//Flash_ReadStat1();
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Flash_WriteEnable();
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FlashSendByte(PAGEPROG);
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@ -403,7 +401,7 @@ uint16_t Flash_WriteDataCont(uint32_t address, uint8_t *in, uint16_t len) {
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}
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bool Flash_WipeMemoryPage(uint8_t page) {
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if (!FlashInit(0)) {
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if (!FlashInit()) {
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if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
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return false;
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}
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@ -417,7 +415,7 @@ bool Flash_WipeMemoryPage(uint8_t page) {
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}
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// Wipes flash memory completely, fills with 0xFF
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bool Flash_WipeMemory() {
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if (!FlashInit(0)) {
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if (!FlashInit()) {
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if ( MF_DBGLEVEL > 3 ) Dbprintf("Flash_WriteData init fail");
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return false;
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}
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@ -498,12 +496,13 @@ void Flash_EraseChip(void) {
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void Flashmem_print_status(void) {
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DbpString("Flash memory");
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Dbprintf(" Baudrate................%dMHz",FLASHMEM_SPIBAUDRATE/1000000);
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if (!FlashInit(0)) {
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DbpString(" init....................FAIL");
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if (!FlashInit()) {
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DbpString(" Init....................FAIL");
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return;
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}
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DbpString(" init....................OK");
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DbpString(" Init....................OK");
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uint8_t dev_id = Flash_ReadID();
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switch (dev_id) {
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