PR feedback and make things work generally

2025-08-20 13:23:51 -07:00 · 2025-02-20 14:51:08 +00:00 · 2025-02-20 14:51:08 +00:00 · 280b3301ee
commit 280b3301ee
parent 46506f04ae
6 changed files with 1 additions and 1 deletions
--- a/fpga/Makefile
+++ b/fpga/Makefile
@ -188,7 +188,7 @@ work:
 	$(Q)$(RM) $@ $*.drc $*.rbt
 	$(info [=] BITGEN $@)
 	$(Q)$(XILINX_TOOLS_PREFIX)bitgen $(VERBOSITY) -w $* $@
-	#python3 ../strip_date_time_from_binary.py $@ || true
+	python3 ../strip_date_time_from_binary.py $@ || true
 	$(Q)$(CP) $@ ..

 # Build all targets
--- a/fpga/fpga_icopyx_hf.bit
+++ b/fpga/fpga_icopyx_hf.bit
--- a/fpga/fpga_pm3_felica.bit
+++ b/fpga/fpga_pm3_felica.bit
--- a/fpga/fpga_pm3_hf.bit
+++ b/fpga/fpga_pm3_hf.bit
--- a/fpga/fpga_pm3_hf_15.bit
+++ b/fpga/fpga_pm3_hf_15.bit
--- a/fpga/fpga_pm3_lf.bit
+++ b/fpga/fpga_pm3_lf.bit