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https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-20 13:23:51 -07:00
FIX: This commit fixes the broken LF since I change the spindelay calls. The original problem is that spindelayus calls is incremented with21.3us each step, making it very hard to find exact timings found in the datasheets for T55x7, HID etcetc. When @marshmellow and I looked into this 2014, I had this on my back of my mind but forgot it since I didn't know how the source code / pm3 worked. This behavior in spindelayus has given the bit-period for ON/OFF measured in (us) very hard to find. Its kind of magic that it worked so far so good. Well until I started to look into the "hf legic" bitbanging ASK ON/OFF keying and that one needs a much more precis timer. Same goes for the PCF7931 code.
I've added a precise timer in the new files ticks.c and moved some older stuff from util.c to have a solid base for this. UNTESTED, and the timings measured for t55x7 in lfops.c and other parts has not been adjusted to this "correct" timer.
This commit is contained in:
iceman1001
parent
8e4021fddc
commit
24c49d36ba
4 changed files with 67 additions and 89 deletions
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@ -60,19 +60,19 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
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while(*command != '\0' && *command != ' ') {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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SpinDelayUs(delay_off);
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WaitUS(delay_off);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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LED_D_ON();
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if(*(command++) == '0')
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SpinDelayUs(period_0); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(period_0);
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else
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SpinDelayUs(period_1); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(period_1);
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}
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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SpinDelayUs(delay_off); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(delay_off);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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@ -225,20 +225,20 @@ void WriteTIbyte(uint8_t b)
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// modulate 8 bits out to the antenna
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for (i=0; i<8; i++)
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{
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if (b&(1<<i)) {
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// stop modulating antenna
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if ( b & ( 1 << i ) ) {
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// stop modulating antenna 1ms
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LOW(GPIO_SSC_DOUT);
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SpinDelayUs(1000); // ICEMAN: problem with (us) clock is 21.3us increments
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// modulate antenna
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HIGH(GPIO_SSC_DOUT);
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SpinDelayUs(1000); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(1000);
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// modulate antenna 1ms
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HIGH(GPIO_SSC_DOUT);
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WaitUS(1000);
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} else {
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// stop modulating antenna
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// stop modulating antenna 1ms
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LOW(GPIO_SSC_DOUT);
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SpinDelayUs(300); // ICEMAN: problem with (us) clock is 21.3us increments
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// modulate antenna
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WaitUS(300);
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// modulate antenna 1m
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HIGH(GPIO_SSC_DOUT);
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SpinDelayUs(1700); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(1700);
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}
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}
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}
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@ -437,7 +437,7 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
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if (gap) {
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WDT_HIT();
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SHORT_COIL();
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SpinDelayUs(gap); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(gap);
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}
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}
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}
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@ -1138,13 +1138,12 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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void TurnReadLFOn(int delay) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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// measure antenna strength.
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//int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
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// where to save it
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SpinDelayCountUs(delay); // ICEMAN: problem with (us) clock is 21.3us increments
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// Give it a bit of time for the resonant antenna to settle.
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WaitUS(delay);
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}
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// Write one bit to card
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@ -1154,7 +1153,7 @@ void T55xxWriteBit(int bit) {
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else
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TurnReadLFOn(WRITE_1);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayCountUs(WRITE_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(WRITE_GAP);
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}
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// Send T5577 reset command then read stream (see if we can identify the start of the stream)
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@ -1168,7 +1167,7 @@ void T55xxResetRead(void) {
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// Trigger T55x7 in mode.
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayCountUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(START_GAP);
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// reset tag - op code 00
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T55xxWriteBit(0);
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@ -1198,7 +1197,7 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
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// Trigger T55x7 in mode.
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayCountUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(START_GAP);
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// Opcode 10
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T55xxWriteBit(1);
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@ -1258,7 +1257,7 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
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// Trigger T55x7 Direct Access Mode with start gap
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayCountUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(START_GAP);
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// Opcode 1[page]
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T55xxWriteBit(1);
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@ -1298,7 +1297,7 @@ void T55xxWakeUp(uint32_t Pwd){
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// Trigger T55x7 Direct Access Mode
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayCountUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(START_GAP);
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// Opcode 10
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T55xxWriteBit(1);
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@ -1629,20 +1628,20 @@ void SendForward(uint8_t fwd_bit_count) {
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fwd_bit_sz--; //prepare next bit modulation
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fwd_write_ptr++;
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
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SpinDelayUs(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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// now start writting
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while(fwd_bit_sz-- > 0) { //prepare next bit modulation
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if(((*fwd_write_ptr++) & 1) == 1)
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SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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else {
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//These timings work for 4469/4269/4305 (with the 55*8 above)
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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SpinDelayUs(23*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(23*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
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SpinDelayUs(9*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(9*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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}
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}
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}
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