mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-19 21:03:48 -07:00
bootrom: fix mix of spaces & tabs
This commit is contained in:
Philippe Teuwen
parent
2d1a077ae4
commit
248a861613
4 changed files with 271 additions and 271 deletions
|
|
@ -16,11 +16,11 @@ extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
|
||||||
extern uint32_t _osimage_entry;
|
extern uint32_t _osimage_entry;
|
||||||
|
|
||||||
void DbpString(char *str) {
|
void DbpString(char *str) {
|
||||||
byte_t len = 0;
|
byte_t len = 0;
|
||||||
while (str[len] != 0x00)
|
while (str[len] != 0x00)
|
||||||
len++;
|
len++;
|
||||||
|
|
||||||
cmd_send(CMD_DEBUG_PRINT_STRING, len, 0, 0, (byte_t*)str, len);
|
cmd_send(CMD_DEBUG_PRINT_STRING, len, 0, 0, (byte_t*)str, len);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void ConfigClocks(void) {
|
static void ConfigClocks(void) {
|
||||||
|
|
@ -30,54 +30,54 @@ static void ConfigClocks(void) {
|
||||||
// enable system clock and USB clock
|
// enable system clock and USB clock
|
||||||
AT91C_BASE_PMC->PMC_SCER |= AT91C_PMC_PCK | AT91C_PMC_UDP;
|
AT91C_BASE_PMC->PMC_SCER |= AT91C_PMC_PCK | AT91C_PMC_UDP;
|
||||||
|
|
||||||
// enable the clock to the following peripherals
|
// enable the clock to the following peripherals
|
||||||
AT91C_BASE_PMC->PMC_PCER =
|
AT91C_BASE_PMC->PMC_PCER =
|
||||||
(1<<AT91C_ID_PIOA) |
|
(1<<AT91C_ID_PIOA) |
|
||||||
(1<<AT91C_ID_ADC) |
|
(1<<AT91C_ID_ADC) |
|
||||||
(1<<AT91C_ID_SPI) |
|
(1<<AT91C_ID_SPI) |
|
||||||
(1<<AT91C_ID_SSC) |
|
(1<<AT91C_ID_SSC) |
|
||||||
(1<<AT91C_ID_PWMC) |
|
(1<<AT91C_ID_PWMC) |
|
||||||
(1<<AT91C_ID_UDP);
|
(1<<AT91C_ID_UDP);
|
||||||
|
|
||||||
// worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
|
// worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
|
||||||
// if SLCK slow clock runs at its worst case (max) frequency of 42khz
|
// if SLCK slow clock runs at its worst case (max) frequency of 42khz
|
||||||
// max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
|
// max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
|
||||||
|
|
||||||
// enable main oscillator and set startup delay
|
// enable main oscillator and set startup delay
|
||||||
AT91C_BASE_PMC->PMC_MOR =
|
AT91C_BASE_PMC->PMC_MOR =
|
||||||
AT91C_CKGR_MOSCEN |
|
AT91C_CKGR_MOSCEN |
|
||||||
PMC_MAIN_OSC_STARTUP_DELAY(8);
|
PMC_MAIN_OSC_STARTUP_DELAY(8);
|
||||||
|
|
||||||
// wait for main oscillator to stabilize
|
// wait for main oscillator to stabilize
|
||||||
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) ) {};
|
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) ) {};
|
||||||
|
|
||||||
// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
|
// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
|
||||||
// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
|
// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
|
||||||
// PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
|
// PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
|
||||||
AT91C_BASE_PMC->PMC_PLLR =
|
AT91C_BASE_PMC->PMC_PLLR =
|
||||||
PMC_PLL_DIVISOR(2) |
|
PMC_PLL_DIVISOR(2) |
|
||||||
//PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
|
//PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
|
||||||
PMC_PLL_COUNT_BEFORE_LOCK(0x3F) |
|
PMC_PLL_COUNT_BEFORE_LOCK(0x3F) |
|
||||||
PMC_PLL_FREQUENCY_RANGE(0) |
|
PMC_PLL_FREQUENCY_RANGE(0) |
|
||||||
PMC_PLL_MULTIPLIER(12) |
|
PMC_PLL_MULTIPLIER(12) |
|
||||||
PMC_PLL_USB_DIVISOR(1);
|
PMC_PLL_USB_DIVISOR(1);
|
||||||
|
|
||||||
// wait for PLL to lock
|
// wait for PLL to lock
|
||||||
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ) {};
|
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ) {};
|
||||||
|
|
||||||
// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
|
// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
|
||||||
// datasheet recommends that this register is programmed in two operations
|
// datasheet recommends that this register is programmed in two operations
|
||||||
// when changing to PLL, program the prescaler first then the source
|
// when changing to PLL, program the prescaler first then the source
|
||||||
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
|
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
|
||||||
|
|
||||||
// wait for main clock ready signal
|
// wait for main clock ready signal
|
||||||
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
|
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
|
||||||
|
|
||||||
// set the source to PLL
|
// set the source to PLL
|
||||||
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
|
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
|
||||||
|
|
||||||
// wait for main clock ready signal
|
// wait for main clock ready signal
|
||||||
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
|
while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
|
||||||
}
|
}
|
||||||
|
|
||||||
static void Fatal(void) {
|
static void Fatal(void) {
|
||||||
|
|
@ -85,140 +85,140 @@ static void Fatal(void) {
|
||||||
}
|
}
|
||||||
|
|
||||||
void UsbPacketReceived(uint8_t *packet, int len) {
|
void UsbPacketReceived(uint8_t *packet, int len) {
|
||||||
int i, dont_ack = 0;
|
int i, dont_ack = 0;
|
||||||
UsbCommand* c = (UsbCommand *)packet;
|
UsbCommand* c = (UsbCommand *)packet;
|
||||||
volatile uint32_t *p;
|
volatile uint32_t *p;
|
||||||
|
|
||||||
//if ( len != sizeof(UsbCommand)) Fatal();
|
//if ( len != sizeof(UsbCommand)) Fatal();
|
||||||
|
|
||||||
uint32_t arg0 = (uint32_t)c->arg[0];
|
uint32_t arg0 = (uint32_t)c->arg[0];
|
||||||
|
|
||||||
switch(c->cmd) {
|
switch(c->cmd) {
|
||||||
case CMD_DEVICE_INFO: {
|
case CMD_DEVICE_INFO: {
|
||||||
dont_ack = 1;
|
dont_ack = 1;
|
||||||
arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
|
arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
|
||||||
DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
|
DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
|
||||||
if(common_area.flags.osimage_present)
|
if(common_area.flags.osimage_present)
|
||||||
arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
|
arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
|
||||||
|
|
||||||
cmd_send(CMD_DEVICE_INFO,arg0,1,2,0,0);
|
cmd_send(CMD_DEVICE_INFO,arg0,1,2,0,0);
|
||||||
} break;
|
} break;
|
||||||
|
|
||||||
case CMD_SETUP_WRITE: {
|
case CMD_SETUP_WRITE: {
|
||||||
/* The temporary write buffer of the embedded flash controller is mapped to the
|
/* The temporary write buffer of the embedded flash controller is mapped to the
|
||||||
* whole memory region, only the last 8 bits are decoded.
|
* whole memory region, only the last 8 bits are decoded.
|
||||||
*/
|
*/
|
||||||
p = (volatile uint32_t *)&_flash_start;
|
p = (volatile uint32_t *)&_flash_start;
|
||||||
for(i = 0; i < 12; i++)
|
for(i = 0; i < 12; i++)
|
||||||
p[i+arg0] = c->d.asDwords[i];
|
p[i+arg0] = c->d.asDwords[i];
|
||||||
} break;
|
} break;
|
||||||
|
|
||||||
case CMD_FINISH_WRITE: {
|
case CMD_FINISH_WRITE: {
|
||||||
uint32_t* flash_mem = (uint32_t*)(&_flash_start);
|
uint32_t* flash_mem = (uint32_t*)(&_flash_start);
|
||||||
for ( int j=0; j<2; j++) {
|
for ( int j=0; j<2; j++) {
|
||||||
for(i = 0+(64*j); i < 64+(64*j); i++) {
|
for(i = 0+(64*j); i < 64+(64*j); i++) {
|
||||||
flash_mem[i] = c->d.asDwords[i];
|
flash_mem[i] = c->d.asDwords[i];
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t flash_address = arg0 + (0x100*j);
|
uint32_t flash_address = arg0 + (0x100*j);
|
||||||
|
|
||||||
/* Check that the address that we are supposed to write to is within our allowed region */
|
/* Check that the address that we are supposed to write to is within our allowed region */
|
||||||
if( ((flash_address + AT91C_IFLASH_PAGE_SIZE - 1) >= end_addr) || (flash_address < start_addr) ) {
|
if( ((flash_address + AT91C_IFLASH_PAGE_SIZE - 1) >= end_addr) || (flash_address < start_addr) ) {
|
||||||
/* Disallow write */
|
/* Disallow write */
|
||||||
dont_ack = 1;
|
dont_ack = 1;
|
||||||
cmd_send(CMD_NACK,0,0,0,0,0);
|
cmd_send(CMD_NACK,0,0,0,0,0);
|
||||||
} else {
|
} else {
|
||||||
uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
|
uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
|
||||||
/* Translate address to flash page and do flash, update here for the 512k part */
|
/* Translate address to flash page and do flash, update here for the 512k part */
|
||||||
AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
|
AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
|
||||||
MC_FLASH_COMMAND_PAGEN(page_n) |
|
MC_FLASH_COMMAND_PAGEN(page_n) |
|
||||||
AT91C_MC_FCMD_START_PROG;
|
AT91C_MC_FCMD_START_PROG;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Wait until flashing of page finishes
|
// Wait until flashing of page finishes
|
||||||
uint32_t sr;
|
uint32_t sr;
|
||||||
while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
|
while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
|
||||||
if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
|
if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
|
||||||
dont_ack = 1;
|
dont_ack = 1;
|
||||||
cmd_send(CMD_NACK,sr,0,0,0,0);
|
cmd_send(CMD_NACK,sr,0,0,0,0);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} break;
|
} break;
|
||||||
|
|
||||||
case CMD_HARDWARE_RESET: {
|
case CMD_HARDWARE_RESET: {
|
||||||
usb_disable();
|
usb_disable();
|
||||||
AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
|
AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
|
||||||
} break;
|
} break;
|
||||||
|
|
||||||
case CMD_START_FLASH: {
|
case CMD_START_FLASH: {
|
||||||
if (c->arg[2] == START_FLASH_MAGIC)
|
if (c->arg[2] == START_FLASH_MAGIC)
|
||||||
bootrom_unlocked = 1;
|
bootrom_unlocked = 1;
|
||||||
else
|
else
|
||||||
bootrom_unlocked = 0;
|
bootrom_unlocked = 0;
|
||||||
|
|
||||||
int prot_start = (int)&_bootrom_start;
|
int prot_start = (int)&_bootrom_start;
|
||||||
int prot_end = (int)&_bootrom_end;
|
int prot_end = (int)&_bootrom_end;
|
||||||
int allow_start = (int)&_flash_start;
|
int allow_start = (int)&_flash_start;
|
||||||
int allow_end = (int)&_flash_end;
|
int allow_end = (int)&_flash_end;
|
||||||
int cmd_start = c->arg[0];
|
int cmd_start = c->arg[0];
|
||||||
int cmd_end = c->arg[1];
|
int cmd_end = c->arg[1];
|
||||||
|
|
||||||
/* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
|
/* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
|
||||||
* bootrom area. In any case they must be within the flash area.
|
* bootrom area. In any case they must be within the flash area.
|
||||||
*/
|
*/
|
||||||
if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start))) &&
|
if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start))) &&
|
||||||
(cmd_start >= allow_start) &&
|
(cmd_start >= allow_start) &&
|
||||||
(cmd_end <= allow_end) ) {
|
(cmd_end <= allow_end) ) {
|
||||||
start_addr = cmd_start;
|
start_addr = cmd_start;
|
||||||
end_addr = cmd_end;
|
end_addr = cmd_end;
|
||||||
} else {
|
} else {
|
||||||
start_addr = end_addr = 0;
|
start_addr = end_addr = 0;
|
||||||
dont_ack = 1;
|
dont_ack = 1;
|
||||||
cmd_send(CMD_NACK,0,0,0,0,0);
|
cmd_send(CMD_NACK,0,0,0,0,0);
|
||||||
}
|
}
|
||||||
} break;
|
} break;
|
||||||
|
|
||||||
default: {
|
default: {
|
||||||
Fatal();
|
Fatal();
|
||||||
} break;
|
} break;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!dont_ack)
|
if (!dont_ack)
|
||||||
cmd_send(CMD_ACK,arg0,0,0,0,0);
|
cmd_send(CMD_ACK,arg0,0,0,0,0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void flash_mode(int externally_entered) {
|
static void flash_mode(int externally_entered) {
|
||||||
start_addr = 0;
|
start_addr = 0;
|
||||||
end_addr = 0;
|
end_addr = 0;
|
||||||
bootrom_unlocked = 0;
|
bootrom_unlocked = 0;
|
||||||
uint8_t rx[sizeof(UsbCommand)];
|
uint8_t rx[sizeof(UsbCommand)];
|
||||||
|
|
||||||
usb_enable();
|
usb_enable();
|
||||||
|
|
||||||
// wait for reset to be complete?
|
// wait for reset to be complete?
|
||||||
for (volatile size_t i=0; i<0x100000; i++) {};
|
for (volatile size_t i=0; i<0x100000; i++) {};
|
||||||
|
|
||||||
for(;;) {
|
for(;;) {
|
||||||
WDT_HIT();
|
WDT_HIT();
|
||||||
|
|
||||||
// Check if there is a usb packet available
|
// Check if there is a usb packet available
|
||||||
if (usb_poll_validate_length()) {
|
if (usb_poll_validate_length()) {
|
||||||
if (usb_read(rx, sizeof(rx)) )
|
if (usb_read(rx, sizeof(rx)) )
|
||||||
UsbPacketReceived(rx, sizeof(rx));
|
UsbPacketReceived(rx, sizeof(rx));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!externally_entered && !BUTTON_PRESS()) {
|
if (!externally_entered && !BUTTON_PRESS()) {
|
||||||
/* Perform a reset to leave flash mode */
|
/* Perform a reset to leave flash mode */
|
||||||
usb_disable();
|
usb_disable();
|
||||||
LED_B_ON();
|
LED_B_ON();
|
||||||
AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
|
AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
|
||||||
for(;;) {};
|
for(;;) {};
|
||||||
}
|
}
|
||||||
if (externally_entered && BUTTON_PRESS()) {
|
if (externally_entered && BUTTON_PRESS()) {
|
||||||
/* Let the user's button press override the automatic leave */
|
/* Let the user's button press override the automatic leave */
|
||||||
externally_entered = 0;
|
externally_entered = 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void BootROM(void) {
|
void BootROM(void) {
|
||||||
|
|
@ -229,54 +229,54 @@ void BootROM(void) {
|
||||||
// Kill all the pullups, especially the one on USB D+; leave them for
|
// Kill all the pullups, especially the one on USB D+; leave them for
|
||||||
// the unused pins, though.
|
// the unused pins, though.
|
||||||
AT91C_BASE_PIOA->PIO_PPUDR =
|
AT91C_BASE_PIOA->PIO_PPUDR =
|
||||||
GPIO_USB_PU |
|
GPIO_USB_PU |
|
||||||
GPIO_LED_A |
|
GPIO_LED_A |
|
||||||
GPIO_LED_B |
|
GPIO_LED_B |
|
||||||
GPIO_LED_C |
|
GPIO_LED_C |
|
||||||
GPIO_LED_D |
|
GPIO_LED_D |
|
||||||
GPIO_FPGA_DIN |
|
GPIO_FPGA_DIN |
|
||||||
GPIO_FPGA_DOUT |
|
GPIO_FPGA_DOUT |
|
||||||
GPIO_FPGA_CCLK |
|
GPIO_FPGA_CCLK |
|
||||||
GPIO_FPGA_NINIT |
|
GPIO_FPGA_NINIT |
|
||||||
GPIO_FPGA_NPROGRAM |
|
GPIO_FPGA_NPROGRAM |
|
||||||
GPIO_FPGA_DONE |
|
GPIO_FPGA_DONE |
|
||||||
GPIO_MUXSEL_HIPKD |
|
GPIO_MUXSEL_HIPKD |
|
||||||
GPIO_MUXSEL_HIRAW |
|
GPIO_MUXSEL_HIRAW |
|
||||||
GPIO_MUXSEL_LOPKD |
|
GPIO_MUXSEL_LOPKD |
|
||||||
GPIO_MUXSEL_LORAW |
|
GPIO_MUXSEL_LORAW |
|
||||||
GPIO_RELAY |
|
GPIO_RELAY |
|
||||||
GPIO_NVDD_ON;
|
GPIO_NVDD_ON;
|
||||||
// (and add GPIO_FPGA_ON)
|
// (and add GPIO_FPGA_ON)
|
||||||
// These pins are outputs
|
// These pins are outputs
|
||||||
AT91C_BASE_PIOA->PIO_OER =
|
AT91C_BASE_PIOA->PIO_OER =
|
||||||
GPIO_LED_A |
|
GPIO_LED_A |
|
||||||
GPIO_LED_B |
|
GPIO_LED_B |
|
||||||
GPIO_LED_C |
|
GPIO_LED_C |
|
||||||
GPIO_LED_D |
|
GPIO_LED_D |
|
||||||
GPIO_RELAY |
|
GPIO_RELAY |
|
||||||
GPIO_NVDD_ON;
|
GPIO_NVDD_ON;
|
||||||
// PIO controls the following pins
|
// PIO controls the following pins
|
||||||
AT91C_BASE_PIOA->PIO_PER =
|
AT91C_BASE_PIOA->PIO_PER =
|
||||||
GPIO_USB_PU |
|
GPIO_USB_PU |
|
||||||
GPIO_LED_A |
|
GPIO_LED_A |
|
||||||
GPIO_LED_B |
|
GPIO_LED_B |
|
||||||
GPIO_LED_C |
|
GPIO_LED_C |
|
||||||
GPIO_LED_D;
|
GPIO_LED_D;
|
||||||
|
|
||||||
// USB_D_PLUS_PULLUP_OFF();
|
// USB_D_PLUS_PULLUP_OFF();
|
||||||
usb_disable();
|
usb_disable();
|
||||||
LED_D_OFF();
|
LED_D_OFF();
|
||||||
LED_C_ON();
|
LED_C_ON();
|
||||||
LED_B_OFF();
|
LED_B_OFF();
|
||||||
LED_A_OFF();
|
LED_A_OFF();
|
||||||
|
|
||||||
// Set the first 256kb memory flashspeed
|
// Set the first 256kb memory flashspeed
|
||||||
AT91C_BASE_EFC0->EFC_FMR = AT91C_MC_FWS_1FWS | MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
|
AT91C_BASE_EFC0->EFC_FMR = AT91C_MC_FWS_1FWS | MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
|
||||||
|
|
||||||
// 9 = 256, 10+ is 512kb
|
// 9 = 256, 10+ is 512kb
|
||||||
uint8_t id = ( *(AT91C_DBGU_CIDR) & 0xF00) >> 8;
|
uint8_t id = ( *(AT91C_DBGU_CIDR) & 0xF00) >> 8;
|
||||||
if ( id > 9 )
|
if ( id > 9 )
|
||||||
AT91C_BASE_EFC1->EFC_FMR = AT91C_MC_FWS_1FWS | MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
|
AT91C_BASE_EFC1->EFC_FMR = AT91C_MC_FWS_1FWS | MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
|
||||||
|
|
||||||
// Initialize all system clocks
|
// Initialize all system clocks
|
||||||
ConfigClocks();
|
ConfigClocks();
|
||||||
|
|
@ -288,36 +288,36 @@ void BootROM(void) {
|
||||||
case AT91C_RSTC_RSTTYP_WATCHDOG:
|
case AT91C_RSTC_RSTTYP_WATCHDOG:
|
||||||
case AT91C_RSTC_RSTTYP_SOFTWARE:
|
case AT91C_RSTC_RSTTYP_SOFTWARE:
|
||||||
case AT91C_RSTC_RSTTYP_USER:
|
case AT91C_RSTC_RSTTYP_USER:
|
||||||
/* In these cases the common_area in RAM should be ok, retain it if it's there */
|
/* In these cases the common_area in RAM should be ok, retain it if it's there */
|
||||||
if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1)
|
if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1)
|
||||||
common_area_present = 1;
|
common_area_present = 1;
|
||||||
break;
|
break;
|
||||||
default: /* Otherwise, initialize it from scratch */
|
default: /* Otherwise, initialize it from scratch */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!common_area_present){
|
if (!common_area_present){
|
||||||
/* Common area not ok, initialize it */
|
/* Common area not ok, initialize it */
|
||||||
int i;
|
int i;
|
||||||
/* Makeshift memset, no need to drag util.c into this */
|
/* Makeshift memset, no need to drag util.c into this */
|
||||||
for(i=0; i<sizeof(common_area); i++)
|
for(i=0; i<sizeof(common_area); i++)
|
||||||
((char*)&common_area)[i] = 0;
|
((char*)&common_area)[i] = 0;
|
||||||
|
|
||||||
common_area.magic = COMMON_AREA_MAGIC;
|
common_area.magic = COMMON_AREA_MAGIC;
|
||||||
common_area.version = 1;
|
common_area.version = 1;
|
||||||
common_area.flags.bootrom_present = 1;
|
common_area.flags.bootrom_present = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
common_area.flags.bootrom_present = 1;
|
common_area.flags.bootrom_present = 1;
|
||||||
if (common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
|
if (common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
|
||||||
common_area.command = COMMON_AREA_COMMAND_NONE;
|
common_area.command = COMMON_AREA_COMMAND_NONE;
|
||||||
flash_mode(1);
|
flash_mode(1);
|
||||||
} else if (BUTTON_PRESS()) {
|
} else if (BUTTON_PRESS()) {
|
||||||
flash_mode(0);
|
flash_mode(0);
|
||||||
} else if (_osimage_entry == 0xffffffffU) {
|
} else if (_osimage_entry == 0xffffffffU) {
|
||||||
flash_mode(1);
|
flash_mode(1);
|
||||||
} else {
|
} else {
|
||||||
// jump to Flash address of the osimage entry point (LSBit set for thumb mode)
|
// jump to Flash address of the osimage entry point (LSBit set for thumb mode)
|
||||||
__asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
|
__asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -12,40 +12,40 @@
|
||||||
|
|
||||||
.global flashstart
|
.global flashstart
|
||||||
flashstart:
|
flashstart:
|
||||||
b reset
|
b reset
|
||||||
b undefined_instruction
|
b undefined_instruction
|
||||||
b software_interrupt
|
b software_interrupt
|
||||||
b prefetch_abort
|
b prefetch_abort
|
||||||
b data_abort
|
b data_abort
|
||||||
b . @reserved
|
b . @reserved
|
||||||
ldr pc, [pc,#-0xF20] @ IRQ - read the AIC
|
ldr pc, [pc,#-0xF20] @ IRQ - read the AIC
|
||||||
b fiq
|
b fiq
|
||||||
|
|
||||||
reset:
|
reset:
|
||||||
ldr sp, =_stack_end @ initialize stack pointer to top of RAM
|
ldr sp, =_stack_end @ initialize stack pointer to top of RAM
|
||||||
|
|
||||||
@ copy bootloader to RAM (in case the user re-flashes the bootloader)
|
@ copy bootloader to RAM (in case the user re-flashes the bootloader)
|
||||||
ldr r0, =__bootphase2_src_start__
|
ldr r0, =__bootphase2_src_start__
|
||||||
ldr r1, =__bootphase2_start__
|
ldr r1, =__bootphase2_start__
|
||||||
ldr r2, =__bootphase2_end__
|
ldr r2, =__bootphase2_end__
|
||||||
1:
|
1:
|
||||||
ldr r3, [r0], #4
|
ldr r3, [r0], #4
|
||||||
str r3, [r1], #4
|
str r3, [r1], #4
|
||||||
cmp r1, r2
|
cmp r1, r2
|
||||||
blo 1b
|
blo 1b
|
||||||
|
|
||||||
ldr r3, =ram_start @ start address of RAM bootloader
|
ldr r3, =ram_start @ start address of RAM bootloader
|
||||||
bx r3 @ jump to it
|
bx r3 @ jump to it
|
||||||
|
|
||||||
.ltorg
|
.ltorg
|
||||||
|
|
||||||
undefined_instruction:
|
undefined_instruction:
|
||||||
b .
|
b .
|
||||||
software_interrupt:
|
software_interrupt:
|
||||||
b .
|
b .
|
||||||
prefetch_abort:
|
prefetch_abort:
|
||||||
b .
|
b .
|
||||||
data_abort:
|
data_abort:
|
||||||
b .
|
b .
|
||||||
fiq:
|
fiq:
|
||||||
b .
|
b .
|
||||||
|
|
|
||||||
|
|
@ -12,52 +12,52 @@ INCLUDE ../common/ldscript.common
|
||||||
|
|
||||||
PHDRS
|
PHDRS
|
||||||
{
|
{
|
||||||
phase1 PT_LOAD;
|
phase1 PT_LOAD;
|
||||||
phase2 PT_LOAD;
|
phase2 PT_LOAD;
|
||||||
bss PT_LOAD;
|
bss PT_LOAD;
|
||||||
}
|
}
|
||||||
|
|
||||||
ENTRY(flashstart)
|
ENTRY(flashstart)
|
||||||
SECTIONS
|
SECTIONS
|
||||||
{
|
{
|
||||||
.bootphase1 : {
|
.bootphase1 : {
|
||||||
*(.startup)
|
*(.startup)
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
_version_information_start = .;
|
_version_information_start = .;
|
||||||
KEEP(*(.version_information));
|
KEEP(*(.version_information));
|
||||||
|
|
||||||
. = LENGTH(bootphase1) - 0x4;
|
. = LENGTH(bootphase1) - 0x4;
|
||||||
LONG(_version_information_start);
|
LONG(_version_information_start);
|
||||||
} >bootphase1 :phase1
|
} >bootphase1 :phase1
|
||||||
|
|
||||||
.bootphase2 : {
|
.bootphase2 : {
|
||||||
*(.startphase2)
|
*(.startphase2)
|
||||||
*(.text)
|
*(.text)
|
||||||
*(.text.*)
|
*(.text.*)
|
||||||
*(.eh_frame)
|
*(.eh_frame)
|
||||||
*(.glue_7)
|
*(.glue_7)
|
||||||
*(.glue_7t)
|
*(.glue_7t)
|
||||||
*(.rodata)
|
*(.rodata)
|
||||||
*(.rodata.*)
|
*(.rodata.*)
|
||||||
*(.data)
|
*(.data)
|
||||||
*(.data.*)
|
*(.data.*)
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
} >ram AT>bootphase2 :phase2
|
} >ram AT>bootphase2 :phase2
|
||||||
|
|
||||||
__bootphase2_src_start__ = LOADADDR(.bootphase2);
|
__bootphase2_src_start__ = LOADADDR(.bootphase2);
|
||||||
__bootphase2_start__ = ADDR(.bootphase2);
|
__bootphase2_start__ = ADDR(.bootphase2);
|
||||||
__bootphase2_end__ = __bootphase2_start__ + SIZEOF(.bootphase2);
|
__bootphase2_end__ = __bootphase2_start__ + SIZEOF(.bootphase2);
|
||||||
|
|
||||||
.bss : {
|
.bss : {
|
||||||
__bss_start__ = .;
|
__bss_start__ = .;
|
||||||
*(.bss)
|
*(.bss)
|
||||||
*(.bss.*)
|
*(.bss.*)
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
__bss_end__ = .;
|
__bss_end__ = .;
|
||||||
} >ram AT>ram :bss
|
} >ram AT>ram :bss
|
||||||
|
|
||||||
.commonarea (NOLOAD) : {
|
.commonarea (NOLOAD) : {
|
||||||
*(.commonarea)
|
*(.commonarea)
|
||||||
} >commonarea
|
} >commonarea
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@
|
||||||
|
|
||||||
.global ram_start
|
.global ram_start
|
||||||
ram_start:
|
ram_start:
|
||||||
ldr sp, =_stack_end
|
ldr sp, =_stack_end
|
||||||
bl BootROM
|
bl BootROM
|
||||||
|
|
||||||
.ltorg
|
.ltorg
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue