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typos

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This commit is contained in:
Philippe Teuwen 2021-10-16 23:43:31 +02:00
commit 232843477c
37 changed files with 115 additions and 129 deletions
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2
fpga-xc3s100e/lo_adc.v
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@ -79,7 +79,7 @@ begin
to_arm_shiftreg <= adc_d;
else begin
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
// simulation showed a glitch occuring due to the LSB of the shifter
// simulation showed a glitch occurring due to the LSB of the shifter
// not being set as we shift bits out
// this ensures the ssp_din remains low after a transfer and suppresses
// the glitch that would occur when the last data shifted out ended in

2
fpga-xc3s100e/lo_read.v
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@ -31,7 +31,7 @@ begin
to_arm_shiftreg <= adc_d;
else begin
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
// simulation showed a glitch occuring due to the LSB of the shifter
// simulation showed a glitch occurring due to the LSB of the shifter
// not being set as we shift bits out
// this ensures the ssp_din remains low after a transfer and suppresses
// the glitch that would occur when the last data shifted out ended in