From 225bb420c658958ba825c09e985a3cb6b31d5bbd Mon Sep 17 00:00:00 2001
From: Christian Zietz <czietz@gmx.net>
Date: Sat, 3 Feb 2024 11:44:18 +0100
Subject: [PATCH] Shorten threshold registers to number of used bits

---
 fpga/fpga_icopyx_hf.bit  | Bin 72749 -> 72749 bytes
 fpga/fpga_pm3_felica.bit | Bin 42176 -> 42176 bytes
 fpga/fpga_pm3_hf.bit     | Bin 42172 -> 42172 bytes
 fpga/fpga_pm3_hf_15.bit  | Bin 42175 -> 42175 bytes
 fpga/fpga_pm3_lf.bit     | Bin 42172 -> 42172 bytes
 fpga/fpga_pm3_top.v      |   8 ++++----
 6 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/fpga/fpga_icopyx_hf.bit b/fpga/fpga_icopyx_hf.bit
index d452201426be520236c9d15f653fde20aa556b61..0bd761f40bd9de223d1045bab8906806717e4eea 100644
GIT binary patch
delta 29
lcmZ3xgJtawmI-#e#tbP8oQ4KgMwV8lCXL=(y%`@#0|1Hg2*CgV

delta 29
lcmZ3xgJtawmI-#eMhqzooQ7srCdO7Krj6cPy%`@#0|1H#2*LmW

diff --git a/fpga/fpga_pm3_felica.bit b/fpga/fpga_pm3_felica.bit
index 140f0a5ea05a27149521a75962d1f646a521cce4..6c3b02e8b533b096c1b972d0d2080f765b0f32e3 100644
GIT binary patch
delta 25
hcmX?blIg%nrU|w@#tbP8oQ4KgMwV7a8$HXH003}_2p0eV

delta 25
hcmX?blIg%nrU|w@MhqzooQ7srCdO8V8$HXH003~72p0eV

diff --git a/fpga/fpga_pm3_hf.bit b/fpga/fpga_pm3_hf.bit
index d6711216cbd233f4cf0c91aaf2fc5f0549b474d9..f59d788fa6b2361cb9818a9c4a57b6f237d16007 100644
GIT binary patch
delta 25
hcmdmUl4;LLrU{lj#tbP8oQ4KgMiy448(qtn003`+2nhfH

delta 25
hcmdmUl4;LLrU{ljMhqzooQ7srCPr2!8(qtn003`}2nhfH

diff --git a/fpga/fpga_pm3_hf_15.bit b/fpga/fpga_pm3_hf_15.bit
index 41e8103d1925ded135f28900b95dd8dcbecea62d..03c3b6b9416f356384d235a07effa7a4779e3fda 100644
GIT binary patch
delta 26
icmdmgl4<`*rU^E@#tbP8oQ4KgMwV6zmK#0GmH+^E2nag>

delta 26
icmdmgl4<`*rU^E@MhqzooQ7srCPr4K78^awmH+^Ej0jHv

diff --git a/fpga/fpga_pm3_lf.bit b/fpga/fpga_pm3_lf.bit
index 363e4cfc657e80f267102fed9efdfa7c625c6e2c..701dfbd555328a54e0639762f080a7f93e430bd5 100644
GIT binary patch
delta 26
icmdmUl4;LLrU{n3#tbP8oQ4KgMiy4aW*gngmH+^DjtD*g

delta 26
icmdmUl4;LLrU{n3MhqzooQ7srCPr39rW@VLmH+^DmIyrn

diff --git a/fpga/fpga_pm3_top.v b/fpga/fpga_pm3_top.v
index 5478125e7..a36cd3e6d 100644
--- a/fpga/fpga_pm3_top.v
+++ b/fpga/fpga_pm3_top.v
@@ -111,8 +111,8 @@ always @(posedge spck) if (~ncs) shift_reg <= {shift_reg[14:0], mosi};
 reg trace_enable;
 
 reg [7:0] lf_ed_threshold;
-reg [10:0] hf_edge_detect_threshold;
-reg [10:0] hf_edge_detect_threshold_high;
+reg [5:0] hf_edge_detect_threshold;
+reg [5:0] hf_edge_detect_threshold_high;
 
 // adjustable frequency clock
 wire [7:0] pck_cnt;
@@ -157,8 +157,8 @@ begin
         `FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
         `FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
         begin
-            hf_edge_detect_threshold <= {6'b0, shift_reg[5:0]};
-            hf_edge_detect_threshold_high <= {6'b0, shift_reg[11:6]};
+            hf_edge_detect_threshold <= shift_reg[5:0];
+            hf_edge_detect_threshold_high <= shift_reg[11:6];
         end
 `endif
     endcase