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This commit is contained in:
Philippe Teuwen 2019-08-06 13:51:10 +02:00
commit 1354aec556
31 changed files with 84 additions and 84 deletions
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8
armsrc/appmain.c
View file

@ -267,9 +267,9 @@ void MeasureAntennaTuning(void) {
SpinDelay(20);
uint32_t adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
if (i == 95)
v_lf125 = adcval; // voltage at 125Khz
v_lf125 = adcval; // voltage at 125kHz
if (i == 89)
v_lf134 = adcval; // voltage at 134Khz
v_lf134 = adcval; // voltage at 134kHz
LF_Results[i] = adcval >> 9; // scale int to fit in byte for graphing purposes
if (LF_Results[i] > peak) {
@ -1956,8 +1956,8 @@ void __attribute__((noreturn)) AppMain(void) {
AT91C_BASE_PIOA->PIO_BSR = GPIO_PCK0;
AT91C_BASE_PIOA->PIO_PDR = GPIO_PCK0;
AT91C_BASE_PMC->PMC_SCER |= AT91C_PMC_PCK0;
// PCK0 is PLL clock / 4 = 96Mhz / 4 = 24Mhz
AT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_4; // 4 for 24Mhz pck0, 2 for 48 MHZ pck0
// PCK0 is PLL clock / 4 = 96MHz / 4 = 24MHz
AT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_4; // 4 for 24MHz pck0, 2 for 48 MHZ pck0
AT91C_BASE_PIOA->PIO_OER = GPIO_PCK0;
// Reset SPI

2
armsrc/felica.c
View file

@ -7,7 +7,7 @@
#include "crc16.h" // crc16 ccitt
// FeliCa timings
// minimum time between the start bits of consecutive transfers from reader to tag: 6800 carrier (13.56Mhz) cycles
// minimum time between the start bits of consecutive transfers from reader to tag: 6800 carrier (13.56MHz) cycles
#ifndef FELICA_REQUEST_GUARD_TIME
# define FELICA_REQUEST_GUARD_TIME (6800/16 + 1)
#endif

2
armsrc/flashmem.c
View file

@ -16,7 +16,7 @@ uint32_t FLASHMEM_SPIBAUDRATE = FLASH_BAUD;
void FlashmemSetSpiBaudrate(uint32_t baudrate) {
FLASHMEM_SPIBAUDRATE = baudrate;
Dbprintf("Spi Baudrate : %dMhz", FLASHMEM_SPIBAUDRATE / 1000000);
Dbprintf("Spi Baudrate : %dMHz", FLASHMEM_SPIBAUDRATE / 1000000);
}
// initialize

4
armsrc/fpgaloader.c
View file

@ -81,7 +81,7 @@ void SetupSpi(int mode) {
AT91C_BASE_SPI->SPI_CSR[0] =
(1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
(1 << 16) | // Delay Before SPCK (1 MCK period)
(6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
(6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24MHz/6 = 4M baud
AT91C_SPI_BITS_16 | // Bits per Transfer (16 bits)
(0 << 3) | // Chip Select inactive after transfer
AT91C_SPI_NCPHA | // Clock Phase data captured on leading edge, changes on following edge
@ -101,7 +101,7 @@ void SetupSpi(int mode) {
AT91C_BASE_SPI->SPI_CSR[2] =
( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
( 1 << 16) | // Delay Before SPCK (1 MCK period)
( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24MHz/6 = 4M baud
AT91C_SPI_BITS_9 | // Bits per Transfer (9 bits)
( 0 << 3) | // Chip Select inactive after transfer
( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge

6
armsrc/hitag2.c
View file

@ -965,7 +965,7 @@ void SimulateHitagTag(bool tag_mem_supplied, uint8_t *data) {
// Set up simulator mode, frequency divisor which will drive the FPGA
// and analog mux selection.
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Configure output pin that is connected to the FPGA (for modulating)
@ -1171,7 +1171,7 @@ void ReaderHitag(hitag_function htf, hitag_data *htd) {
// Set fpga in edge detect with reader field, we can modulate as reader now
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Configure output and enable pin that is connected to the FPGA (for modulating)
@ -1442,7 +1442,7 @@ void WriterHitag(hitag_function htf, hitag_data *htd, int page) {
// Set fpga in edge detect with reader field, we can modulate as reader now
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Disable modulation at default, which means enable the field

8
armsrc/hitagS.c
View file

@ -983,7 +983,7 @@ void SimulateHitagSTag(bool tag_mem_supplied, uint8_t *data) {
// and analog mux selection.
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Configure output pin that is connected to the FPGA (for modulating)
@ -1182,7 +1182,7 @@ void ReadHitagS(hitag_function htf, hitag_data *htd) {
// Set fpga in edge detect with reader field, we can modulate as reader now
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Configure output and enable pin that is connected to the FPGA (for modulating)
@ -1517,7 +1517,7 @@ void WritePageHitagS(hitag_function htf, hitag_data *htd, int page) {
// Set fpga in edge detect with reader field, we can modulate as reader now
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Disable modulation at default, which means enable the field
@ -1778,7 +1778,7 @@ void check_challenges(bool file_given, uint8_t *data) {
// Set fpga in edge detect with reader field, we can modulate as reader now
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Disable modulation at default, which means enable the field

2
armsrc/iso14443a.c
View file

@ -25,7 +25,7 @@ static uint8_t iso14_pcb_blocknum = 0;
//
// ISO14443 timing:
//
// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56MHz) cycles
#define REQUEST_GUARD_TIME (7000/16 + 1)
// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)

4
armsrc/iso15693.c
View file

@ -32,8 +32,8 @@
//
// VICC (tag) -> VCD (reader)
// Modulation:
// ASK / one subcarrier (423,75 khz)
// FSK / two subcarriers (423,75 khz && 484,28 khz)
// ASK / one subcarrier (423,75 kHz)
// FSK / two subcarriers (423,75 kHz && 484,28 kHz)
// Data Rates / Modes:
// low ASK: 6,62 kbit/s
// low FSK: 6.67 kbit/s

28
armsrc/lfops.c
View file

@ -33,7 +33,7 @@ still benefit from this repo. This is why its configurable and we use to set th
// VALUES TAKEN FROM EM4x function: SendForward
// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
// START_GAP = 440; (55*8) cycles at 125kHz (8us = 1cycle)
// WRITE_GAP = 128; (16*8)
// WRITE_1 = 256 32*8; (32*8)
@ -374,7 +374,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint
}
// hack2 needed--- it appears to take about 8-16us to turn the antenna back on
// leading to ~ 1 to 2 125khz samples extra in every off period
// leading to ~ 1 to 2 125kHz samples extra in every off period
// so we should test for last 0 before next 1 and reduce period_0 by this extra amount...
// but is this time different for every antenna or other hw builds??? more testing needed
@ -447,9 +447,9 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint
void ReadTItag(void) {
StartTicks();
// some hardcoded initial params
// when we read a TI tag we sample the zerocross line at 2Mhz
// TI tags modulate a 1 as 16 cycles of 123.2Khz
// TI tags modulate a 0 as 16 cycles of 134.2Khz
// when we read a TI tag we sample the zerocross line at 2MHz
// TI tags modulate a 1 as 16 cycles of 123.2kHz
// TI tags modulate a 0 as 16 cycles of 134.2kHz
#define FSAMPLE 2000000
#define FREQLO 123200
#define FREQHI 134200
@ -465,9 +465,9 @@ void ReadTItag(void) {
// when to tell if we're close enough to one freq or another
uint32_t threshold = (sampleslo - sampleshi + 1) >> 1;
// TI tags charge at 134.2Khz
// TI tags charge at 134.2kHz
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
// Place FPGA in passthrough mode, in this mode the CROSS_LO line
// connects to SSP_DIN and the SSP_DOUT logic level controls
@ -693,8 +693,8 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) {
}
Dbprintf("Writing to tag: %x%08x, crc=%x", idhi, idlo, crc);
// TI tags charge at 134.2Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
// TI tags charge at 134.2kHz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
// Place FPGA in passthrough mode, in this mode the CROSS_LO line
// connects to SSP_DIN and the SSP_DOUT logic level controls
// whether we're modulating the antenna (high)
@ -767,9 +767,9 @@ void SimulateTagLowFrequencyEx(int period, int gap, bool ledcontrol, int numcycl
sample_config *sc = getSamplingConfig();
if ((sc->divisor == 1) || (sc->divisor < 0) || (sc->divisor > 255))
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
else if (sc->divisor == 0)
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
else
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
@ -1195,7 +1195,7 @@ void CmdHIDdemodFSK(int findone, uint32_t *high, uint32_t *low, int ledcontrol)
size_t size;
uint32_t hi2 = 0, hi = 0, lo = 0;
int dummyIdx = 0;
// Configure to go in 125Khz listen mode
// Configure to go in 125kHz listen mode
LFSetupFPGAForADC(95, true);
//clear read buffer
@ -1446,7 +1446,7 @@ void CmdIOdemodFSK(int findone, uint32_t *high, uint32_t *low, int ledcontrol) {
BigBuf_Clear_keep_EM();
// Configure to go in 125Khz listen mode
// Configure to go in 125kHz listen mode
LFSetupFPGAForADC(95, true);
while (!BUTTON_PRESS() && !data_available()) {
@ -2254,7 +2254,7 @@ uint8_t *fwd_write_ptr; //forwardlink bit pointer
//====================================================================
//--------------------------------------------------------------------
// VALUES TAKEN FROM EM4x function: SendForward
// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
// START_GAP = 440; (55*8) cycles at 125kHz (8us = 1cycle)
// WRITE_GAP = 128; (16*8)
// WRITE_1 = 256 32*8; (32*8)

6
armsrc/lfsampling.c
View file

@ -13,7 +13,7 @@ Default LF config is set to:
decimation = 1 (we keep 1 out of 1 samples)
bits_per_sample = 8
averaging = YES
divisor = 95 (125khz)
divisor = 95 (125kHz)
trigger_threshold = 0
*/
sample_config config = { 1, 8, 1, 95, 0 } ;
@ -83,9 +83,9 @@ void pushBit(BitstreamOut *stream, uint8_t bit) {
void LFSetupFPGAForADC(int divisor, bool lf_field) {
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
if ((divisor == 1) || (divisor < 0) || (divisor > 255))
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
else if (divisor == 0)
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
else
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);

2
armsrc/pcf7931.c
View file

@ -404,7 +404,7 @@ void SendCmdPCF7931(uint32_t *tab) {
Dbprintf("Sending data frame...");
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
LED_A_ON();

8
armsrc/ticks.c
View file

@ -10,8 +10,8 @@
//-----------------------------------------------------------------------------
#include "ticks.h"
// timer counts in 21.3uS increments (1024/48Mhz), rounding applies
// WARNING: timer can't measure more than 1.39s (21.3uS * 0xffff)
// timer counts in 21.3us increments (1024/48MHz), rounding applies
// WARNING: timer can't measure more than 1.39s (21.3us * 0xffff)
void SpinDelayUs(int us) {
int ticks = ((MCK / 1000000) * us + 512) >> 10;
@ -35,13 +35,13 @@ void SpinDelayUs(int us) {
}
}
// WARNING: timer can't measure more than 1.39s (21.3uS * 0xffff)
// WARNING: timer can't measure more than 1.39s (21.3us * 0xffff)
void SpinDelay(int ms) {
if (ms > 1390) {
Dbprintf(_RED_("Error, SpinDelay called with %i > 1390"), ms);
ms = 1390;
}
// convert to uS and call microsecond delay function
// convert to us and call microsecond delay function
SpinDelayUs(ms * 1000);
}
// -------------------------------------------------------------------------

8
armsrc/util.c
View file

@ -176,8 +176,8 @@ void SpinUp(uint32_t speed) {
// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
int BUTTON_CLICKED(int ms) {
// Up to 500ms in between clicks to mean a double click
// timer counts in 21.3uS increments (1024/48Mhz)
// WARNING: timer can't measure more than 1.39s (21.3uS * 0xffff)
// timer counts in 21.3us increments (1024/48MHz)
// WARNING: timer can't measure more than 1.39s (21.3us * 0xffff)
if (ms > 1390) {
Dbprintf(_RED_("Error, BUTTON_CLICKED called with %i > 1390"), ms);
ms = 1390;
@ -240,8 +240,8 @@ int BUTTON_CLICKED(int ms) {
// Determine if a button is held down
int BUTTON_HELD(int ms) {
// timer counts in 21.3uS increments (1024/48Mhz)
// WARNING: timer can't measure more than 1.39s (21.3uS * 0xffff)
// timer counts in 21.3us increments (1024/48MHz)
// WARNING: timer can't measure more than 1.39s (21.3us * 0xffff)
if (ms > 1390) {
Dbprintf(_RED_("Error, BUTTON_HELD called with %i > 1390"), ms);
ms = 1390;

10
bootrom/bootrom.c
View file

@ -52,7 +52,7 @@ void DbpString(char *str) {
static void ConfigClocks(void) {
// we are using a 16 MHz crystal as the basis for everything
// slow clock runs at 32Khz typical regardless of crystal
// slow clock runs at 32kHz typical regardless of crystal
// enable system clock and USB clock
AT91C_BASE_PMC->PMC_SCER |= AT91C_PMC_PCK | AT91C_PMC_UDP;
@ -66,8 +66,8 @@ static void ConfigClocks(void) {
(1 << AT91C_ID_PWMC) |
(1 << AT91C_ID_UDP);
// worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
// if SLCK slow clock runs at its worst case (max) frequency of 42khz
// worst case scenario, with MAINCK = 16MHz xtal, startup delay is 1.4ms
// if SLCK slow clock runs at its worst case (max) frequency of 42kHz
// max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
// enable main oscillator and set startup delay
@ -80,7 +80,7 @@ static void ConfigClocks(void) {
// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
// PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
// PLL output is MAINCK * multiplier / divisor = 16MHz * 12 / 2 = 96MHz
AT91C_BASE_PMC->PMC_PLLR =
PMC_PLL_DIVISOR(2) |
//PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
@ -92,7 +92,7 @@ static void ConfigClocks(void) {
// wait for PLL to lock
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) {};
// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
// we want a master clock (MCK) to be PLL clock / 2 = 96MHz / 2 = 48MHz
// datasheet recommends that this register is programmed in two operations
// when changing to PLL, program the prescaler first then the source
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;

2
client/cmddata.c
View file

@ -1611,7 +1611,7 @@ int CmdTuneSamples(const char *Cmd) {
}
if (test1 > 0) {
PrintAndLogEx(SUCCESS, "\nDisplaying LF tuning graph. Divisor 89 is 134khz, 95 is 125khz.\n\n");
PrintAndLogEx(SUCCESS, "\nDisplaying LF tuning graph. Divisor 89 is 134kHz, 95 is 125kHz.\n\n");
GraphTraceLen = 256;
ShowGraphWindow();
RepaintGraphWindow();

6
client/cmdflashmem.c
View file

@ -29,9 +29,9 @@ static int usage_flashmem_spibaud(void) {
PrintAndLogEx(NORMAL, " h this help");
PrintAndLogEx(NORMAL, " <baudrate> SPI baudrate in MHz [24|48]");
PrintAndLogEx(NORMAL, " ");
PrintAndLogEx(NORMAL, " If >= 24Mhz, FASTREADS instead of READS instruction will be used.");
PrintAndLogEx(NORMAL, " Reading Flash ID will virtually always fail under 48Mhz setting");
PrintAndLogEx(NORMAL, " Unless you know what you are doing, please stay at 24Mhz");
PrintAndLogEx(NORMAL, " If >= 24MHz, FASTREADS instead of READS instruction will be used.");
PrintAndLogEx(NORMAL, " Reading Flash ID will virtually always fail under 48MHz setting");
PrintAndLogEx(NORMAL, " Unless you know what you are doing, please stay at 24MHz");
PrintAndLogEx(NORMAL, "Examples:");
PrintAndLogEx(NORMAL, " mem spibaud 48");
return PM3_SUCCESS;

4
client/cmdhw.c
View file

@ -449,7 +449,7 @@ static int CmdSetDivisor(const char *Cmd) {
PrintAndLogEx(ERR, "divisor must be between 19 and 255");
return PM3_EINVARG;
}
// 12 000 000 (12Mhz)
// 12 000 000 (12MHz)
clearCommandBuffer();
SendCommandNG(CMD_LF_SET_DIVISOR, (uint8_t *)&arg, sizeof(arg));
PrintAndLogEx(SUCCESS, "Divisor set, expected %.1f kHz", ((double)12000 / (arg + 1)));
@ -596,7 +596,7 @@ static command_t CommandTable[] = {
{"ping", CmdPing, IfPm3Present, "Test if the Proxmark3 is responsive"},
{"readmem", CmdReadmem, IfPm3Present, "[address] -- Read memory at decimal address from flash"},
{"reset", CmdReset, IfPm3Present, "Reset the Proxmark3"},
{"setlfdivisor", CmdSetDivisor, IfPm3Present, "<19 - 255> -- Drive LF antenna at 12Mhz/(divisor+1)"},
{"setlfdivisor", CmdSetDivisor, IfPm3Present, "<19 - 255> -- Drive LF antenna at 12MHz/(divisor+1)"},
{"setmux", CmdSetMux, IfPm3Present, "Set the ADC mux to a specific value"},
{"standalone", CmdStandalone, IfPm3Present, "Jump to the standalone mode"},
{"status", CmdStatus, IfPm3Present, "Show runtime status information about the connected Proxmark3"},

8
client/cmdsmartcard.c
View file

@ -61,7 +61,7 @@ static int usage_sm_upgrade(void) {
static int usage_sm_setclock(void) {
PrintAndLogEx(NORMAL, "Usage: sc setclock [h] c <clockspeed>");
PrintAndLogEx(NORMAL, " h : this help");
PrintAndLogEx(NORMAL, " c <> : clockspeed (0 = 16mhz, 1=8mhz, 2=4mhz) ");
PrintAndLogEx(NORMAL, " c <> : clockspeed (0 = 16MHz, 1=8MHz, 2=4MHz) ");
PrintAndLogEx(NORMAL, "");
PrintAndLogEx(NORMAL, "Examples:");
PrintAndLogEx(NORMAL, " sc setclock c 2");
@ -843,13 +843,13 @@ static int CmdSmartSetClock(const char *Cmd) {
switch (clock1) {
case 0:
PrintAndLogEx(SUCCESS, "Clock changed to 16mhz giving 10800 baudrate");
PrintAndLogEx(SUCCESS, "Clock changed to 16MHz giving 10800 baudrate");
break;
case 1:
PrintAndLogEx(SUCCESS, "Clock changed to 8mhz giving 21600 baudrate");
PrintAndLogEx(SUCCESS, "Clock changed to 8MHz giving 21600 baudrate");
break;
case 2:
PrintAndLogEx(SUCCESS, "Clock changed to 4mhz giving 86400 baudrate");
PrintAndLogEx(SUCCESS, "Clock changed to 4MHz giving 86400 baudrate");
break;
default:
break;

4
client/cmdtrace.c
View file

@ -804,9 +804,9 @@ int CmdTraceList(const char *Cmd) {
} else {
PrintAndLogEx(NORMAL, "Start = Start of Start Bit, End = End of last modulation. Src = Source of Transfer");
if (protocol == ISO_14443A || protocol == PROTO_MIFARE || protocol == MFDES || protocol == TOPAZ)
PrintAndLogEx(NORMAL, "ISO14443A - All times are in carrier periods (1/13.56Mhz)");
PrintAndLogEx(NORMAL, "ISO14443A - All times are in carrier periods (1/13.56MHz)");
if (protocol == THINFILM)
PrintAndLogEx(NORMAL, "Thinfilm - All times are in carrier periods (1/13.56Mhz)");
PrintAndLogEx(NORMAL, "Thinfilm - All times are in carrier periods (1/13.56MHz)");
if (protocol == ICLASS)
PrintAndLogEx(NORMAL, "iClass - Timings are not as accurate");
if (protocol == LEGIC)

4
common/i2c.c
View file

@ -26,7 +26,7 @@
volatile unsigned long c;
// Direct use the loop to delay. 6 instructions loop, Masterclock 48Mhz,
// Direct use the loop to delay. 6 instructions loop, Masterclock 48MHz,
// delay=1 is about 200kbps
// timer.
// I2CSpinDelayClk(4) = 12.31us
@ -41,7 +41,7 @@ void __attribute__((optimize("O0"))) I2CSpinDelayClk(uint16_t delay) {
#define ISO7618_MAX_FRAME 255
// try i2c bus recovery at 100kHz = 5uS high, 5uS low
// try i2c bus recovery at 100kHz = 5us high, 5us low
void I2C_recovery(void) {
DbpString("Performing i2c bus recovery");

8
common/iso15693tools.h
View file

@ -82,8 +82,8 @@ char *Iso15693sprintUID(char *target, uint8_t *uid);
// SOF defined as
// 1) Unmodulated time of 56.64us
// 2) 24 pulses of 423.75khz
// 3) logic '1' (unmodulated for 18.88us followed by 8 pulses of 423.75khz)
// 2) 24 pulses of 423.75kHz
// 3) logic '1' (unmodulated for 18.88us followed by 8 pulses of 423.75kHz)
static const int Iso15693FrameSOF[] = {
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
@ -109,8 +109,8 @@ static const int Iso15693Logic1[] = {
};
// EOF defined as
// 1) logic '0' (8 pulses of 423.75khz followed by unmodulated for 18.88us)
// 2) 24 pulses of 423.75khz
// 1) logic '0' (8 pulses of 423.75kHz followed by unmodulated for 18.88us)
// 2) 24 pulses of 423.75kHz
// 3) Unmodulated time of 56.64us
static const int Iso15693FrameEOF[] = {
1, 1, 1, 1,

4
common/usb_cdc.c
View file

@ -446,8 +446,8 @@ AT91S_CDC_LINE_CODING line = { // purely informative, actual values don't matter
8 // 8 Data bits
};
// timer counts in 21.3uS increments (1024/48Mhz), rounding applies
// WARNING: timer can't measure more than 1.39s (21.3uS * 0xffff)
// timer counts in 21.3us increments (1024/48MHz), rounding applies
// WARNING: timer can't measure more than 1.39s (21.3us * 0xffff)
static void SpinDelay(int ms) {
int us = ms * 1000;
int ticks = ((MCK / 1000000) * us + 512) >> 10;

2
fpga/hi_simulate.v
View file

@ -69,7 +69,7 @@ begin
// Get next bit at 212kHz
ssp_clk <= ssp_clk_divider[5];
else
// Get next bit at 424Khz
// Get next bit at 424kHz
ssp_clk <= ssp_clk_divider[4];
end

2
fpga/lf_edge_detect.v
View file

@ -5,7 +5,7 @@
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// input clk is 24Mhz
// input clk is 24MHz
`include "min_max_tracker.v"
module lf_edge_detect(input clk, input [7:0] adc_d, input [7:0] lf_ed_threshold,

2
fpga/lo_adc.v
View file

@ -48,7 +48,7 @@ assign dbg = adc_clk;
assign adc_clk = ~clk_state;
// serialized SSP data is gated by clk_state to suppress unwanted signal
assign ssp_din = to_arm_shiftreg[7] && !clk_state;
// SSP clock always runs at 24Mhz
// SSP clock always runs at 24MHz
assign ssp_clk = pck0;
// SSP frame is gated by clk_state and goes high when pck_divider=8..15
assign ssp_frame = (pck_divider[7:3] == 5'd1) && !clk_state;

4
fpga/lo_read.v
View file

@ -19,7 +19,7 @@ module lo_read(
reg [7:0] to_arm_shiftreg;
// this task also runs at pck0 frequency (24Mhz) and is used to serialize
// this task also runs at pck0 frequency (24MHz) and is used to serialize
// the ADC output which is then clocked into the ARM SSP.
// because pck_divclk always transitions when pck_cnt = 0 we use the
@ -55,7 +55,7 @@ end
// serialized SSP data is gated by ant_lo to suppress unwanted signal
assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
// SSP clock always runs at 24Mhz
// SSP clock always runs at 24MHz
assign ssp_clk = pck0;
// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;

2
fpga/lp20khz_1MSa_iir_filter.v
View file

@ -28,7 +28,7 @@
// https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html
module lp20khz_1MSa_iir_filter(input clk, input [7:0] adc_d, output rdy, output [7:0] out);
// clk is 24Mhz, the IIR filter is designed for 1MS/s
// clk is 24MHz, the IIR filter is designed for 1MS/s
// hence we need to divide it by 24
// using a shift register takes less area than a counter
reg [23:0] cnt = 1;

2
fpga/testbed_hi_read_tx.v
View file

@ -1,7 +1,7 @@
`include "hi_read_tx.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type

2
fpga/testbed_hi_simulate.v
View file

@ -1,7 +1,7 @@
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type

10
fpga/testbed_lo_read.v
View file

@ -1,14 +1,14 @@
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
lo_is_125khz - input freq selector (1=125kHz, 0=136kHz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ssp_clk - output SSP clock signal 1MHz/1.09MHz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
@ -90,9 +90,9 @@ module testbed_lo_read;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
divisor = 255; //min 16, 95=125kHz, max 255
// simulate 4 A/D cycles at 125Khz
// simulate 4 A/D cycles at 125kHz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end

4
fpga/testbed_lo_simulate.v
View file

@ -1,7 +1,7 @@
`include "lo_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
@ -74,7 +74,7 @@ module testbed_lo_simulate;
// main clock
always #5 pck0 = !pck0;
//cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)
//cross_lo is not really synced to pck0 but it's roughly pck0/192 (24MHz/192=125kHz)
task crank_dut;
begin
@(posedge pck0) ;