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typos

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This commit is contained in:
Philippe Teuwen 2019-08-06 13:51:10 +02:00
commit 1354aec556
31 changed files with 84 additions and 84 deletions
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4
fpga/testbed_lo_simulate.v
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@ -1,7 +1,7 @@
`include "lo_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
@ -74,7 +74,7 @@ module testbed_lo_simulate;
// main clock
always #5 pck0 = !pck0;
//cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)
//cross_lo is not really synced to pck0 but it's roughly pck0/192 (24MHz/192=125kHz)
task crank_dut;
begin
@(posedge pck0) ;