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This commit is contained in:
Philippe Teuwen 2019-08-06 13:51:10 +02:00
commit 1354aec556
31 changed files with 84 additions and 84 deletions
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fpga/testbed_hi_simulate.v
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@ -1,7 +1,7 @@
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type