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typos

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This commit is contained in:
Philippe Teuwen 2019-08-06 13:51:10 +02:00
commit 1354aec556
31 changed files with 84 additions and 84 deletions
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fpga/hi_simulate.v
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@ -69,7 +69,7 @@ begin
// Get next bit at 212kHz
ssp_clk <= ssp_clk_divider[5];
else
// Get next bit at 424Khz
// Get next bit at 424kHz
ssp_clk <= ssp_clk_divider[4];
end