typos

fpga/hi_simulate.v

@@ -69,7 +69,7 @@ begin
       // Get next bit at 212kHz
       ssp_clk <= ssp_clk_divider[5];
     else
-      // Get next bit at 424Khz
+      // Get next bit at 424kHz
       ssp_clk <= ssp_clk_divider[4];
 end
 

fpga/lf_edge_detect.v

@@ -5,7 +5,7 @@
 // at your option, any later version. See the LICENSE.txt file for the text of
 // the license.
 //-----------------------------------------------------------------------------
-// input clk is 24Mhz
+// input clk is 24MHz
 `include "min_max_tracker.v"
 
 module lf_edge_detect(input clk, input [7:0] adc_d, input [7:0] lf_ed_threshold,

fpga/lo_adc.v

@@ -48,7 +48,7 @@ assign dbg = adc_clk;
 assign adc_clk = ~clk_state;
 // serialized SSP data is gated by clk_state to suppress unwanted signal
 assign ssp_din = to_arm_shiftreg[7] && !clk_state;
-// SSP clock always runs at 24Mhz
+// SSP clock always runs at 24MHz
 assign ssp_clk = pck0;
 // SSP frame is gated by clk_state and goes high when pck_divider=8..15
 assign ssp_frame = (pck_divider[7:3] == 5'd1) && !clk_state;

fpga/lo_read.v

@@ -19,7 +19,7 @@ module lo_read(
 
 reg [7:0] to_arm_shiftreg;
 
-// this task also runs at pck0 frequency (24Mhz) and is used to serialize
+// this task also runs at pck0 frequency (24MHz) and is used to serialize
 // the ADC output which is then clocked into the ARM SSP.
 
 // because pck_divclk always transitions when pck_cnt = 0 we use the
@@ -55,7 +55,7 @@ end
 
 // serialized SSP data is gated by ant_lo to suppress unwanted signal
 assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
-// SSP clock always runs at 24Mhz
+// SSP clock always runs at 24MHz
 assign ssp_clk = pck0;
 // SSP frame is gated by ant_lo and goes high when pck_divider=8..15
 assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;

fpga/lp20khz_1MSa_iir_filter.v

@@ -28,7 +28,7 @@
 // https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html
 module lp20khz_1MSa_iir_filter(input clk, input [7:0] adc_d, output rdy, output [7:0] out);
 
-    // clk is 24Mhz, the IIR filter is designed for 1MS/s
+    // clk is 24MHz, the IIR filter is designed for 1MS/s
     // hence we need to divide it by 24
     // using a shift register takes less area than a counter
     reg [23:0] cnt = 1;

fpga/testbed_hi_read_tx.v

@@ -1,7 +1,7 @@
 `include "hi_read_tx.v"
 
 /*
-    pck0            - input main 24Mhz clock (PLL / 4)
+    pck0            - input main 24MHz clock (PLL / 4)
     [7:0] adc_d     - input data from A/D converter
     shallow_modulation  - modulation type
 

fpga/testbed_hi_simulate.v

@@ -1,7 +1,7 @@
 `include "hi_simulate.v"
 
 /*
-    pck0            - input main 24Mhz clock (PLL / 4)
+    pck0            - input main 24MHz clock (PLL / 4)
     [7:0] adc_d     - input data from A/D converter
     mod_type    - modulation type
 

fpga/testbed_lo_read.v

@@ -1,14 +1,14 @@
 `include "lo_read.v"
 /*
-    pck0            - input main 24Mhz clock (PLL / 4)
+    pck0            - input main 24MHz clock (PLL / 4)
     [7:0] adc_d     - input data from A/D converter
-    lo_is_125khz    - input freq selector (1=125Khz, 0=136Khz)
+    lo_is_125khz    - input freq selector (1=125kHz, 0=136kHz)
 
     pwr_lo          - output to coil drivers (ssp_clk / 8)
     adc_clk         - output A/D clock signal
     ssp_frame       - output SSS frame indicator (goes high while the 8 bits are shifted)
     ssp_din         - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
-    ssp_clk         - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
+    ssp_clk         - output SSP clock signal 1MHz/1.09MHz (pck0 / 2*(11+lo_is_125khz) )
 
     ck_1356meg      - input unused
     ck_1356megb     - input unused
@@ -90,9 +90,9 @@ module testbed_lo_read;
         adc_d = 0;
         ssp_dout = 0;
         lo_is_125khz = 1;
-        divisor = 255;  //min 16, 95=125Khz, max 255
+        divisor = 255;  //min 16, 95=125kHz, max 255
 
-        // simulate 4 A/D cycles at 125Khz
+        // simulate 4 A/D cycles at 125kHz
         for (i = 0 ;  i < 8 ;  i = i + 1) begin
             crank_dut;
         end

fpga/testbed_lo_simulate.v

@@ -1,7 +1,7 @@
 `include "lo_simulate.v"
 
 /*
-    pck0            - input main 24Mhz clock (PLL / 4)
+    pck0            - input main 24MHz clock (PLL / 4)
     [7:0] adc_d     - input data from A/D converter
 
 
@@ -74,7 +74,7 @@ module testbed_lo_simulate;
     // main clock
     always #5 pck0 = !pck0;
 
-    //cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)
+    //cross_lo is not really synced to pck0 but it's roughly pck0/192 (24MHz/192=125kHz)
     task crank_dut;
     begin
         @(posedge pck0) ;