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typos
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31 changed files with 84 additions and 84 deletions
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@ -13,7 +13,7 @@ Default LF config is set to:
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decimation = 1 (we keep 1 out of 1 samples)
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bits_per_sample = 8
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averaging = YES
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divisor = 95 (125khz)
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divisor = 95 (125kHz)
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trigger_threshold = 0
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*/
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sample_config config = { 1, 8, 1, 95, 0 } ;
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@ -83,9 +83,9 @@ void pushBit(BitstreamOut *stream, uint8_t bit) {
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void LFSetupFPGAForADC(int divisor, bool lf_field) {
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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if ((divisor == 1) || (divisor < 0) || (divisor > 255))
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
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else if (divisor == 0)
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
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else
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
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