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FPGA Hi-Simulate: Freed up 4 LUTs

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AntiCat 2018-09-05 22:23:22 +02:00
commit 0994c91888
1 changed files with 4 additions and 14 deletions
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18
fpga/hi_simulate.v
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@ -62,22 +62,12 @@ reg ssp_clk;
always @(negedge adc_clk) always @(negedge adc_clk)
begin begin
//If we're in 101, we only need a new bit every 8th carrier bit (53Hz). Otherwise, get next bit at 424Khz
if(mod_type == 3'b101) if(mod_type == 3'b101)
begin // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
if(ssp_clk_divider[7:0] == 8'b00000000) ssp_clk <= ssp_clk_divider[7];
ssp_clk <= 1'b0;
if(ssp_clk_divider[7:0] == 8'b10000000)
ssp_clk <= 1'b1;
end
else else
begin // Get next bit at 424Khz
if(ssp_clk_divider[4:0] == 5'd0)//[4:0] == 5'b00000) ssp_clk <= ssp_clk_divider[4]
ssp_clk <= 1'b1;
if(ssp_clk_divider[4:0] == 5'd16) //[4:0] == 5'b10000)
ssp_clk <= 1'b0;
end
end end