From 07fffb46450a6c08c7ab2f5d1bb2e82e443d6cd1 Mon Sep 17 00:00:00 2001
From: iceman1001 <iceman@iuse.se>
Date: Tue, 26 Sep 2017 17:04:53 +0200
Subject: [PATCH] CHG: bootrom configuration to highest clock PLL

---
 bootrom/bootrom.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/bootrom/bootrom.c b/bootrom/bootrom.c
index c53f2bfc1..94327b0ad 100644
--- a/bootrom/bootrom.c
+++ b/bootrom/bootrom.c
@@ -55,7 +55,8 @@ static void ConfigClocks(void) {
     // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
     AT91C_BASE_PMC->PMC_PLLR =
     	PMC_PLL_DIVISOR(2) |
-		PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
+		//PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
+		PMC_PLL_COUNT_BEFORE_LOCK(0x3F) |
 		PMC_PLL_FREQUENCY_RANGE(0) |
 		PMC_PLL_MULTIPLIER(12) |
 		PMC_PLL_USB_DIVISOR(1);