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iso15 sniff: commit some unused FPGA FSK code for history
This commit is contained in:
Yann GASCUEL
parent
38d49097f9
commit
07013a5aaf
1 changed files with 240 additions and 6 deletions
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@ -37,6 +37,130 @@ begin
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pwr_hi <= 'b0;
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end
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reg [4:0] adc_cnt = 5'd0;
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always @(negedge adc_clk)
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begin
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adc_cnt <= adc_cnt + 1'd1;
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end
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reg [7:0] out1 = 8'd0;
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reg [7:0] out2 = 8'd0;
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reg [7:0] avg = 8'd0;
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reg [7:0] avg1 = 8'd0;
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reg [7:0] avg2 = 8'd0;
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reg [7:0] avg3 = 8'd0;
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reg [7:0] avg4 = 8'd0;
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reg [7:0] avg5 = 8'd0;
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reg [7:0] avg6 = 8'd0;
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reg [7:0] avg7 = 8'd0;
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reg [7:0] avg8 = 8'd0;
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reg [7:0] avg9 = 8'd0;
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reg [7:0] avg10 = 8'd0;
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reg [7:0] avg11 = 8'd0;
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reg [7:0] avg12 = 8'd0;
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reg [7:0] avg13 = 8'd0;
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reg [7:0] avg14 = 8'd0;
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reg [7:0] avg15 = 8'd0;
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reg [7:0] avg16 = 8'd0;
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reg [7:0] diff28 = 8'd0;
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reg [7:0] diff32 = 8'd0;
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reg [11:0] match32 = 12'd0;
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reg [11:0] match28 = 12'd0;
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always @(negedge adc_clk)
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begin
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if (adc_cnt[0] == 1'b0) // every 4 clock
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begin
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avg = adc_d[7:1];
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end
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else
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begin
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avg = avg + adc_d[7:1];
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if (adc_cnt[0] == 1'b1) // every 4 clock
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begin
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if (avg > avg14)
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diff28 = avg - avg14;
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else
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diff28 = avg14 - avg;
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if (avg > avg16)
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diff32 = avg - avg16;
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else
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diff32 = avg16 - avg;
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avg16 = avg15;
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avg15 = avg14;
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avg14 = avg13;
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avg13 = avg12;
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avg12 = avg11;
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avg11 = avg10;
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avg10 = avg9;
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avg9 = avg8;
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avg8 = avg7;
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avg7 = avg6;
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avg6 = avg5;
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avg5 = avg4;
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avg4 = avg3;
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avg3 = avg2;
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avg2 = avg1;
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avg1 = avg;
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if (adc_cnt[4:1] == 4'b0000) // every 32 clock (8*4)
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begin
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match28 = diff28;
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match32 = diff32;
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end
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else
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begin
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match28 = match28 + diff28;
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match32 = match32 + diff32;
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if (adc_cnt[4:1] == 4'b1111) // every 32 clock (8*4)
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begin
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if (match28[11:3] > 10'b0 || match32[11:3] > 10'b0) // if not only noise
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begin
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if (match28 < match32)
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begin
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//if (match32 - match28 < 12'd24)
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//out1 = out1; // out1 stay at is old value
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//else
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if (match32 - match28 > 12'd32)
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out1 = 8'd28;
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else if (match32 - match28 < 12'd16)
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out1 = 8'd0;
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end
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else //if (match32 <= match28)
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begin
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//if (match28 - match32 < 12'd24)
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//out1 = 8'd30; // out1 stay at is old value
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//else
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if (match28 - match32 > 12'd32)
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out1 = 8'd32;
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else if (match28 - match32 < 12'd16)
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out1 = 8'd0;
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end
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end
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else
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begin
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out1 = 8'd0;
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//out2 = match32[8:1];
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end
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//out1 = match28[7:0];
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//out2 = match32[7:0];
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//out2 = 8'hFF;
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//out2 = out1;
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end
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end
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end
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end
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end
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/*
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reg [7:0] adc_cnt = 8'd0;
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reg [7:0] out1 = 8'd0;
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reg [7:0] old = 8'd0;
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@ -80,9 +204,107 @@ begin
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old <= adc_d;
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end
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*/
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// Other version of FSK reader, probably better but not working yet...
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/*reg [7:0] out1 = 8'd0;
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//reg [7:0] old = 8'd0;
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reg [5:0] old1 = 4'd0;
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reg [5:0] old2 = 4'd0;
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//reg [7:0] edge_id = 8'd0;
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//reg edge_started = 1'd0;
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reg [5:0] edge_cnt = 6'd0;
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reg [3:0] last_values = 4'd0;
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// Count clock edge between two signal edges
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always @(negedge adc_clk)
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begin
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edge_cnt <= edge_cnt + 1'd1;
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last_values[3:1] <= last_values[2:0];
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// last_values[0] <= (& adc_d[7:5]); // adc_d >= 192
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last_values[0] <= (adc_d[7:2] > old1 && old1 > old2);
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//out1[7:4] <= out1[3:0];
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//out1[3:0] <= last_values;
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//out1 <= 8'd28;
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//out1 <= out1+1;
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if (edge_cnt > 6'd22 || out1 == 8'd0)
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begin
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if ((last_values[3:2] == 2'b0) && (last_values[1:0] == 2'b11)) // edge start detected
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begin // 2 not high (low or mid) values followed by 2 high values
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out1 <= edge_cnt;
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edge_cnt <= 6'd0;
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end
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else if (edge_cnt > 6'd44) // average(32, 2*28) == 44 : ideal value for iso15 FSK
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begin // /!\ MIN FREQ SUPPORTED = 13MHz/44 ~= 308kHz /!\
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out1 <= 8'd0;
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edge_cnt <= 6'd0;
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end
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end
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old2 <= old1;
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old1 <= adc_d[7:2];
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/*if (last_values[0])
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out1 <= 8'h7F;
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else if (last_values[1])
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out1 <= 8'hFF;
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else
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out1 <= 8'h0;
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/*
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if (& adc_d[7:5] && !(& old[7:5])) // up
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begin
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if (edge_started == 1'd0) // new edge starting
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begin
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//if (edge_id <= edge_cnt)
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// out1 <= edge_cnt - edge_id;
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//else
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// out1 <= edge_cnt + (9'h100 - edge_id);
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out1 <= edge_cnt;
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//edge_id <= edge_cnt;
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edge_started = 1'd1;
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edge_cnt <= 8'd0;
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end
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end
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else
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begin
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edge_started = 1'd0;
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if (edge_cnt > 8'd80)
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begin
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out1 <= 8'd0;
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//edge_id <= 8'd0;
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edge_cnt <= 8'd0;
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end
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*//* if (edge_id <= edge_cnt) // NO EDGE
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begin
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if (edge_cnt - edge_id > 8'd40)
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begin
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out1 <= 8'd0;
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edge_id <= 8'd0;
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edge_cnt <= 8'd0;
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end
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end
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else
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begin
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if (edge_cnt + (9'h100 - edge_id) > 8'd40) // NO EDGE
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begin
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out1 <= 8'd0;
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edge_id <= 8'd0;
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edge_cnt <= 8'd0;
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end
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end*//*
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//end
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//old <= adc_d;
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end*/
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// agregate out values (depending on selected output frequency)
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reg [10:0] out_tmp = 11'd0;
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/*reg [10:0] out_tmp = 11'd0;
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reg [7:0] out = 8'd0;
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always @(negedge adc_clk)
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begin
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@ -104,8 +326,14 @@ begin
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end
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else // 1695_KHZ
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out <= out1;
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end
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// if (adc_cnt > 8'd192 && edge_id < 8'd64) // WUT ?
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// begin
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// out <= 8'd0;
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// out_tmp <= 11'd0;
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// end
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end
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*/
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// Set output (ssp) clock
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(* clock_signal = "yes" *) reg ssp_clk;
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always @(ck_1356meg)
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@ -121,20 +349,26 @@ begin
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end
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// Transmit output
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reg [379:0] megatmpout = 380'd0;
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reg ssp_frame;
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reg [7:0] ssp_out = 8'd0;
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reg [2:0] ssp_cnt = 4'd0;
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reg [3:0] ssp_cnt = 4'd0;
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always @(posedge ssp_clk)
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begin
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ssp_cnt <= ssp_cnt + 1'd1;
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if(ssp_cnt == 3'd15)
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if (ssp_cnt[2:0] == 3'd7)
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begin
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ssp_out <= out;
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ssp_out = {2'b0, megatmpout[379:378], megatmpout[378], megatmpout[378], 2'b0};
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megatmpout[379:2] = megatmpout[377:0];
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megatmpout[1:0] = out2[5:4];
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out2 = out1;
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ssp_frame <= 1'b1;
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end
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else
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begin
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ssp_out <= {ssp_out[6:0], 1'b0};
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ssp_out = {ssp_out[6:0], 1'b0};
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ssp_frame <= 1'b0;
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end
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end
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