mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-21 13:53:55 -07:00
make style
This commit is contained in:
Philippe Teuwen
parent
0d9223a547
commit
0373696662
483 changed files with 56514 additions and 52451 deletions
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@ -16,7 +16,7 @@
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#include "legic_prng.h" /* legic PRNG impl */
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#include "legic.h" /* legic_card_select_t struct */
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static uint8_t* legic_mem; /* card memory, used for sim */
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static uint8_t *legic_mem; /* card memory, used for sim */
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static legic_card_select_t card;/* metadata of currently selected card */
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static crc_t legic_crc;
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@ -58,13 +58,14 @@ static uint32_t last_frame_end; /* ts of last bit of previews rx or tx frame */
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//-----------------------------------------------------------------------------
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// Returns true if a pulse/pause is received within timeout
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static inline bool wait_for(bool value, const uint32_t timeout) {
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while ((bool)(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN) != value) {
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if (GetCountSspClk() > timeout) {
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return false;
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static inline bool wait_for(bool value, const uint32_t timeout)
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{
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while ((bool)(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN) != value) {
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if (GetCountSspClk() > timeout) {
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return false;
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}
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}
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}
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return true;
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return true;
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}
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// Returns a demedulated bit or -1 on code violation
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@ -76,30 +77,31 @@ static inline bool wait_for(bool value, const uint32_t timeout) {
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// - A bit length >80.2us is a 1
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// - A bit length <80.2us is a 0
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// - A bit length >148.6us is a code violation
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static inline int8_t rx_bit() {
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// backup ts for threshold calculation
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uint32_t bit_start = last_frame_end;
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static inline int8_t rx_bit()
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{
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// backup ts for threshold calculation
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uint32_t bit_start = last_frame_end;
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// wait for pause to end
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if (!wait_for(RWD_PULSE, bit_start + RWD_TIME_1*3/2)) {
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return -1;
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}
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// wait for pause to end
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if (!wait_for(RWD_PULSE, bit_start + RWD_TIME_1 * 3 / 2)) {
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return -1;
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}
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// wait for next pause
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if (!wait_for(RWD_PAUSE, bit_start + RWD_TIME_1*3/2)) {
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return -1;
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}
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// wait for next pause
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if (!wait_for(RWD_PAUSE, bit_start + RWD_TIME_1 * 3 / 2)) {
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return -1;
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}
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// update bit and frame end
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last_frame_end = GetCountSspClk();
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// update bit and frame end
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last_frame_end = GetCountSspClk();
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// check for code violation (bit to short)
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if (last_frame_end - bit_start < RWD_TIME_PAUSE) {
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return -1;
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}
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// check for code violation (bit to short)
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if (last_frame_end - bit_start < RWD_TIME_PAUSE) {
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return -1;
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}
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// apply threshold (average of RWD_TIME_0 and )
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return (last_frame_end - bit_start > (RWD_TIME_0 + RWD_TIME_1) / 2);
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// apply threshold (average of RWD_TIME_0 and )
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return (last_frame_end - bit_start > (RWD_TIME_0 + RWD_TIME_1) / 2);
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}
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//-----------------------------------------------------------------------------
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@ -119,21 +121,22 @@ static inline int8_t rx_bit() {
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// Note: The Subcarrier is not disabled during bits to prevent glitches. This is
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// not mandatory but results in a cleaner signal. tx_frame will disable
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// the subcarrier when the frame is done.
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static inline void tx_bit(bool bit) {
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LED_C_ON();
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static inline void tx_bit(bool bit)
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{
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LED_C_ON();
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if (bit) {
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// modulate subcarrier
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HIGH(GPIO_SSC_DOUT);
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} else {
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// do not modulate subcarrier
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LOW(GPIO_SSC_DOUT);
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}
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if (bit) {
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// modulate subcarrier
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HIGH(GPIO_SSC_DOUT);
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} else {
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// do not modulate subcarrier
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LOW(GPIO_SSC_DOUT);
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}
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// wait for tx timeslot to end
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last_frame_end += TAG_BIT_PERIOD;
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while (GetCountSspClk() < last_frame_end) { };
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LED_C_OFF();
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// wait for tx timeslot to end
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last_frame_end += TAG_BIT_PERIOD;
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while (GetCountSspClk() < last_frame_end) { };
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LED_C_OFF();
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}
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//-----------------------------------------------------------------------------
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@ -146,49 +149,51 @@ static inline void tx_bit(bool bit) {
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// and depends only the command received (IV, ACK, READ or WRITE).
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//-----------------------------------------------------------------------------
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static void tx_frame(uint32_t frame, uint8_t len) {
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// wait for next tx timeslot
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last_frame_end += TAG_FRAME_WAIT;
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legic_prng_forward(TAG_FRAME_WAIT/TAG_BIT_PERIOD - 1);
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while (GetCountSspClk() < last_frame_end) { };
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static void tx_frame(uint32_t frame, uint8_t len)
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{
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// wait for next tx timeslot
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last_frame_end += TAG_FRAME_WAIT;
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legic_prng_forward(TAG_FRAME_WAIT / TAG_BIT_PERIOD - 1);
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while (GetCountSspClk() < last_frame_end) { };
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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// transmit frame, MSB first
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for (uint8_t i = 0; i < len; ++i) {
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bool bit = (frame >> i) & 0x01;
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tx_bit(bit ^ legic_prng_get_bit());
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legic_prng_forward(1);
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};
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// transmit frame, MSB first
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for (uint8_t i = 0; i < len; ++i) {
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bool bit = (frame >> i) & 0x01;
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tx_bit(bit ^ legic_prng_get_bit());
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legic_prng_forward(1);
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};
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// disable subcarrier
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LOW(GPIO_SSC_DOUT);
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// disable subcarrier
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LOW(GPIO_SSC_DOUT);
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// log
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uint8_t cmdbytes[] = {len, BYTEx(frame, 0), BYTEx(frame, 1)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, false);
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// log
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uint8_t cmdbytes[] = {len, BYTEx(frame, 0), BYTEx(frame, 1)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, false);
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}
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static void tx_ack() {
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// wait for ack timeslot
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last_frame_end += TAG_ACK_WAIT;
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legic_prng_forward(TAG_ACK_WAIT/TAG_BIT_PERIOD - 1);
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while (GetCountSspClk() < last_frame_end) { };
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static void tx_ack()
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{
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// wait for ack timeslot
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last_frame_end += TAG_ACK_WAIT;
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legic_prng_forward(TAG_ACK_WAIT / TAG_BIT_PERIOD - 1);
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while (GetCountSspClk() < last_frame_end) { };
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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// transmit ack (ack is not encrypted)
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tx_bit(true);
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legic_prng_forward(1);
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// transmit ack (ack is not encrypted)
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tx_bit(true);
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legic_prng_forward(1);
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// disable subcarrier
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LOW(GPIO_SSC_DOUT);
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// disable subcarrier
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LOW(GPIO_SSC_DOUT);
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// log
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uint8_t cmdbytes[] = {1, 1};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, false);
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// log
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uint8_t cmdbytes[] = {1, 1};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, false);
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}
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// Returns a demedulated frame or -1 on code violation
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@ -198,126 +203,129 @@ static void tx_ack() {
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// - forward prng based on ts/TAG_BIT_PERIOD
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// - receive the frame
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// - detect end of frame (last pause)
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static int32_t rx_frame(uint8_t *len) {
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int32_t frame = 0;
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static int32_t rx_frame(uint8_t *len)
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{
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int32_t frame = 0;
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// add 2 SSP clock cycles (1 for tx and 1 for rx pipeline delay)
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// those will be substracted at the end of the rx phase
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last_frame_end -= 2;
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// add 2 SSP clock cycles (1 for tx and 1 for rx pipeline delay)
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// those will be substracted at the end of the rx phase
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last_frame_end -= 2;
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// wait for first pause (start of frame)
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for (uint8_t i = 0; true; ++i) {
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// increment prng every TAG_BIT_PERIOD
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last_frame_end += TAG_BIT_PERIOD;
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legic_prng_forward(1);
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// wait for first pause (start of frame)
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for (uint8_t i = 0; true; ++i) {
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// increment prng every TAG_BIT_PERIOD
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last_frame_end += TAG_BIT_PERIOD;
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legic_prng_forward(1);
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// if start of frame was received exit delay loop
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if (wait_for(RWD_PAUSE, last_frame_end)) {
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last_frame_end = GetCountSspClk();
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break;
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// if start of frame was received exit delay loop
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if (wait_for(RWD_PAUSE, last_frame_end)) {
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last_frame_end = GetCountSspClk();
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break;
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}
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// check for code violation
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if (i > RWD_CMD_TIMEOUT) {
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return -1;
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}
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}
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// check for code violation
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if (i > RWD_CMD_TIMEOUT) {
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return -1;
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}
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}
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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// receive frame
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for (*len = 0; true; ++(*len)) {
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// receive next bit
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LED_B_ON();
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int8_t bit = rx_bit();
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LED_B_OFF();
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// receive frame
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for (*len = 0; true; ++(*len)) {
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// receive next bit
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LED_B_ON();
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int8_t bit = rx_bit();
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LED_B_OFF();
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// check for code violation and to short / long frame
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if ((bit < 0) && ((*len < RWD_MIN_FRAME_LEN) || (*len > RWD_MAX_FRAME_LEN))) {
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return -1;
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}
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// check for code violation and to short / long frame
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if ((bit < 0) && ((*len < RWD_MIN_FRAME_LEN) || (*len > RWD_MAX_FRAME_LEN))) {
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return -1;
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// check for code violation caused by end of frame
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if (bit < 0) {
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break;
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}
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// append bit
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frame |= (bit ^ legic_prng_get_bit()) << (*len);
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legic_prng_forward(1);
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}
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// check for code violation caused by end of frame
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if (bit < 0) {
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break;
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}
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// rx_bit sets coordination timestamp to start of pause, append pause duration
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// and substract 2 SSP clock cycles (1 for rx and 1 for tx pipeline delay) to
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// obtain exact end of frame.
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last_frame_end += RWD_TIME_PAUSE - 2;
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// append bit
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frame |= (bit ^ legic_prng_get_bit()) << (*len);
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legic_prng_forward(1);
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}
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// rx_bit sets coordination timestamp to start of pause, append pause duration
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// and substract 2 SSP clock cycles (1 for rx and 1 for tx pipeline delay) to
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// obtain exact end of frame.
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last_frame_end += RWD_TIME_PAUSE - 2;
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// log
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uint8_t cmdbytes[] = {*len, BYTEx(frame, 0), BYTEx(frame, 1), BYTEx(frame, 2)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, true);
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return frame;
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// log
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uint8_t cmdbytes[] = {*len, BYTEx(frame, 0), BYTEx(frame, 1), BYTEx(frame, 2)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, true);
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return frame;
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}
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//-----------------------------------------------------------------------------
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// Legic Simulator
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//-----------------------------------------------------------------------------
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static int32_t init_card(uint8_t cardtype, legic_card_select_t *p_card) {
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p_card->tagtype = cardtype;
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static int32_t init_card(uint8_t cardtype, legic_card_select_t *p_card)
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{
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p_card->tagtype = cardtype;
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switch (p_card->tagtype) {
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case 0:
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p_card->cmdsize = 6;
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p_card->addrsize = 5;
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p_card->cardsize = 22;
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break;
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case 1:
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p_card->cmdsize = 9;
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p_card->addrsize = 8;
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p_card->cardsize = 256;
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break;
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case 2:
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p_card->cmdsize = 11;
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p_card->addrsize = 10;
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p_card->cardsize = 1024;
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break;
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default:
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p_card->cmdsize = 0;
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p_card->addrsize = 0;
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p_card->cardsize = 0;
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return 2;
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}
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return 0;
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switch (p_card->tagtype) {
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case 0:
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p_card->cmdsize = 6;
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p_card->addrsize = 5;
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p_card->cardsize = 22;
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break;
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case 1:
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p_card->cmdsize = 9;
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p_card->addrsize = 8;
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p_card->cardsize = 256;
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break;
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case 2:
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p_card->cmdsize = 11;
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p_card->addrsize = 10;
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p_card->cardsize = 1024;
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break;
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default:
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p_card->cmdsize = 0;
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p_card->addrsize = 0;
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p_card->cardsize = 0;
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return 2;
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}
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return 0;
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}
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static void init_tag() {
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// configure FPGA
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR
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| FPGA_HF_SIMULATOR_MODULATE_212K);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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static void init_tag()
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{
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// configure FPGA
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR
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| FPGA_HF_SIMULATOR_MODULATE_212K);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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// configure SSC with defaults
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FpgaSetupSsc();
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// configure SSC with defaults
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FpgaSetupSsc();
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// first pull output to low to prevent glitches then re-claim GPIO_SSC_DOUT
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LOW(GPIO_SSC_DOUT);
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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// first pull output to low to prevent glitches then re-claim GPIO_SSC_DOUT
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LOW(GPIO_SSC_DOUT);
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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// reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
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legic_mem = BigBuf_get_EM_addr();
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// reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
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legic_mem = BigBuf_get_EM_addr();
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// start trace
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clear_trace();
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set_tracing(true);
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// start trace
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clear_trace();
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set_tracing(true);
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// init crc calculator
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crc_init(&legic_crc, 4, 0x19 >> 1, 0x05, 0);
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// init crc calculator
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crc_init(&legic_crc, 4, 0x19 >> 1, 0x05, 0);
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// start 212kHz timer (running from SSP Clock)
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StartCountSspClk();
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// start 212kHz timer (running from SSP Clock)
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StartCountSspClk();
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}
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// Setup reader to card connection
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@ -326,119 +334,122 @@ static void init_tag() {
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// - Receive initialisation vector 7 bits
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// - Transmit card type 6 bits
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// - Receive Acknowledge 6 bits
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static int32_t setup_phase(legic_card_select_t *p_card) {
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uint8_t len = 0;
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static int32_t setup_phase(legic_card_select_t *p_card)
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{
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uint8_t len = 0;
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// init coordination timestamp
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last_frame_end = GetCountSspClk();
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// init coordination timestamp
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last_frame_end = GetCountSspClk();
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// reset prng
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legic_prng_init(0);
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// reset prng
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legic_prng_init(0);
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// wait for iv
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int32_t iv = rx_frame(&len);
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if ((len != 7) || (iv < 0)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// configure prng
|
||||
legic_prng_init(iv);
|
||||
|
||||
// reply with card type
|
||||
switch (p_card->tagtype) {
|
||||
case 0:
|
||||
tx_frame(0x0D, 6);
|
||||
break;
|
||||
case 1:
|
||||
tx_frame(0x1D, 6);
|
||||
break;
|
||||
case 2:
|
||||
tx_frame(0x3D, 6);
|
||||
break;
|
||||
}
|
||||
|
||||
// wait for ack
|
||||
int32_t ack = rx_frame(&len);
|
||||
if ((len != 6) || (ack < 0)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// validate data
|
||||
switch (p_card->tagtype) {
|
||||
case 0:
|
||||
if(ack != 0x19) return -1;
|
||||
break;
|
||||
case 1:
|
||||
if(ack != 0x39) return -1;
|
||||
break;
|
||||
case 2:
|
||||
if(ack != 0x39) return -1;
|
||||
break;
|
||||
}
|
||||
|
||||
// During rx the prng is clocked using the variable reader period.
|
||||
// Since rx_frame detects end of frame by detecting a code violation,
|
||||
// the prng is off by one bit period after each rx phase. Hence, tx
|
||||
// code advances the prng by (TAG_FRAME_WAIT/TAG_BIT_PERIOD - 1).
|
||||
// This is not possible for back to back rx, so this quirk reduces
|
||||
// the gap by one period.
|
||||
last_frame_end += TAG_BIT_PERIOD;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint8_t calc_crc4(uint16_t cmd, uint8_t cmd_sz, uint8_t value) {
|
||||
crc_clear(&legic_crc);
|
||||
crc_update(&legic_crc, (value << cmd_sz) | cmd, 8 + cmd_sz);
|
||||
return crc_finish(&legic_crc);
|
||||
}
|
||||
|
||||
static int32_t connected_phase(legic_card_select_t *p_card) {
|
||||
uint8_t len = 0;
|
||||
|
||||
// wait for command
|
||||
int32_t cmd = rx_frame(&len);
|
||||
if (cmd < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// check if command is LEGIC_READ
|
||||
if (len == p_card->cmdsize) {
|
||||
// prepare data
|
||||
uint8_t byte = legic_mem[cmd >> 1];
|
||||
uint8_t crc = calc_crc4(cmd, p_card->cmdsize, byte);
|
||||
|
||||
// transmit data
|
||||
tx_frame((crc << 8) | byte, 12);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
// check if command is LEGIC_WRITE
|
||||
if (len == p_card->cmdsize + 8 + 4) {
|
||||
// decode data
|
||||
uint16_t mask = (1 << p_card->addrsize) - 1;
|
||||
uint16_t addr = (cmd >> 1) & mask;
|
||||
uint8_t byte = (cmd >> p_card->cmdsize) & 0xff;
|
||||
uint8_t crc = (cmd >> (p_card->cmdsize + 8)) & 0xf;
|
||||
|
||||
// check received against calculated crc
|
||||
uint8_t calc_crc = calc_crc4(addr << 1, p_card->cmdsize, byte);
|
||||
if (calc_crc != crc) {
|
||||
Dbprintf("!!! crc mismatch: %x != %x !!!", calc_crc, crc);
|
||||
return -1;
|
||||
// wait for iv
|
||||
int32_t iv = rx_frame(&len);
|
||||
if ((len != 7) || (iv < 0)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// store data
|
||||
legic_mem[addr] = byte;
|
||||
// configure prng
|
||||
legic_prng_init(iv);
|
||||
|
||||
// transmit ack
|
||||
tx_ack();
|
||||
// reply with card type
|
||||
switch (p_card->tagtype) {
|
||||
case 0:
|
||||
tx_frame(0x0D, 6);
|
||||
break;
|
||||
case 1:
|
||||
tx_frame(0x1D, 6);
|
||||
break;
|
||||
case 2:
|
||||
tx_frame(0x3D, 6);
|
||||
break;
|
||||
}
|
||||
|
||||
// wait for ack
|
||||
int32_t ack = rx_frame(&len);
|
||||
if ((len != 6) || (ack < 0)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// validate data
|
||||
switch (p_card->tagtype) {
|
||||
case 0:
|
||||
if (ack != 0x19) return -1;
|
||||
break;
|
||||
case 1:
|
||||
if (ack != 0x39) return -1;
|
||||
break;
|
||||
case 2:
|
||||
if (ack != 0x39) return -1;
|
||||
break;
|
||||
}
|
||||
|
||||
// During rx the prng is clocked using the variable reader period.
|
||||
// Since rx_frame detects end of frame by detecting a code violation,
|
||||
// the prng is off by one bit period after each rx phase. Hence, tx
|
||||
// code advances the prng by (TAG_FRAME_WAIT/TAG_BIT_PERIOD - 1).
|
||||
// This is not possible for back to back rx, so this quirk reduces
|
||||
// the gap by one period.
|
||||
last_frame_end += TAG_BIT_PERIOD;
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
static uint8_t calc_crc4(uint16_t cmd, uint8_t cmd_sz, uint8_t value)
|
||||
{
|
||||
crc_clear(&legic_crc);
|
||||
crc_update(&legic_crc, (value << cmd_sz) | cmd, 8 + cmd_sz);
|
||||
return crc_finish(&legic_crc);
|
||||
}
|
||||
|
||||
static int32_t connected_phase(legic_card_select_t *p_card)
|
||||
{
|
||||
uint8_t len = 0;
|
||||
|
||||
// wait for command
|
||||
int32_t cmd = rx_frame(&len);
|
||||
if (cmd < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// check if command is LEGIC_READ
|
||||
if (len == p_card->cmdsize) {
|
||||
// prepare data
|
||||
uint8_t byte = legic_mem[cmd >> 1];
|
||||
uint8_t crc = calc_crc4(cmd, p_card->cmdsize, byte);
|
||||
|
||||
// transmit data
|
||||
tx_frame((crc << 8) | byte, 12);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
// check if command is LEGIC_WRITE
|
||||
if (len == p_card->cmdsize + 8 + 4) {
|
||||
// decode data
|
||||
uint16_t mask = (1 << p_card->addrsize) - 1;
|
||||
uint16_t addr = (cmd >> 1) & mask;
|
||||
uint8_t byte = (cmd >> p_card->cmdsize) & 0xff;
|
||||
uint8_t crc = (cmd >> (p_card->cmdsize + 8)) & 0xf;
|
||||
|
||||
// check received against calculated crc
|
||||
uint8_t calc_crc = calc_crc4(addr << 1, p_card->cmdsize, byte);
|
||||
if (calc_crc != crc) {
|
||||
Dbprintf("!!! crc mismatch: %x != %x !!!", calc_crc, crc);
|
||||
return -1;
|
||||
}
|
||||
|
||||
// store data
|
||||
legic_mem[addr] = byte;
|
||||
|
||||
// transmit ack
|
||||
tx_ack();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
|
|
@ -447,39 +458,40 @@ static int32_t connected_phase(legic_card_select_t *p_card) {
|
|||
// Only this function is public / called from appmain.c
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
void LegicRfSimulate(uint8_t cardtype) {
|
||||
// configure ARM and FPGA
|
||||
init_tag();
|
||||
void LegicRfSimulate(uint8_t cardtype)
|
||||
{
|
||||
// configure ARM and FPGA
|
||||
init_tag();
|
||||
|
||||
// verify command line input
|
||||
if (init_card(cardtype, &card) != 0) {
|
||||
DbpString("Unknown tagtype.");
|
||||
goto OUT;
|
||||
}
|
||||
|
||||
LED_A_ON();
|
||||
DbpString("Starting Legic emulator, press button to end");
|
||||
while (!BUTTON_PRESS() && !usb_poll_validate_length()) {
|
||||
WDT_HIT();
|
||||
|
||||
// wait for carrier, restart after timeout
|
||||
if (!wait_for(RWD_PULSE, GetCountSspClk() + TAG_BIT_PERIOD)) {
|
||||
continue;
|
||||
// verify command line input
|
||||
if (init_card(cardtype, &card) != 0) {
|
||||
DbpString("Unknown tagtype.");
|
||||
goto OUT;
|
||||
}
|
||||
|
||||
// wait for connection, restart on error
|
||||
if (setup_phase(&card)) {
|
||||
continue;
|
||||
}
|
||||
LED_A_ON();
|
||||
DbpString("Starting Legic emulator, press button to end");
|
||||
while (!BUTTON_PRESS() && !usb_poll_validate_length()) {
|
||||
WDT_HIT();
|
||||
|
||||
// conection is established, process commands until one fails
|
||||
while (!connected_phase(&card)) {
|
||||
WDT_HIT();
|
||||
// wait for carrier, restart after timeout
|
||||
if (!wait_for(RWD_PULSE, GetCountSspClk() + TAG_BIT_PERIOD)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// wait for connection, restart on error
|
||||
if (setup_phase(&card)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// conection is established, process commands until one fails
|
||||
while (!connected_phase(&card)) {
|
||||
WDT_HIT();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
OUT:
|
||||
DbpString("Stopped");
|
||||
switch_off();
|
||||
StopTicks();
|
||||
DbpString("Stopped");
|
||||
switch_off();
|
||||
StopTicks();
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue