mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-21 13:53:55 -07:00
make style
This commit is contained in:
Philippe Teuwen
parent
0d9223a547
commit
0373696662
483 changed files with 56514 additions and 52451 deletions
644
armsrc/legicrf.c
644
armsrc/legicrf.c
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@ -16,7 +16,7 @@
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#include "legic_prng.h" /* legic PRNG impl */
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#include "legic.h" /* legic_card_select_t struct */
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static uint8_t* legic_mem; /* card memory, used for read, write */
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static uint8_t *legic_mem; /* card memory, used for read, write */
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static legic_card_select_t card;/* metadata of currently selected card */
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static crc_t legic_crc;
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@ -50,21 +50,22 @@ static uint32_t last_frame_end; /* ts of last bit of previews rx or tx frame */
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#define WRITE_LOWERLIMIT 4 /* UID and MCC are not writable */
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#define INPUT_THRESHOLD 8 /* heuristically determined, lower values */
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/* lead to detecting false ack during write */
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/* lead to detecting false ack during write */
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//-----------------------------------------------------------------------------
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// I/O interface abstraction (FPGA -> ARM)
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//-----------------------------------------------------------------------------
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static inline uint8_t rx_byte_from_fpga() {
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for(;;) {
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WDT_HIT();
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static inline uint8_t rx_byte_from_fpga()
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{
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for (;;) {
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WDT_HIT();
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// wait for byte be become available in rx holding register
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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return AT91C_BASE_SSC->SSC_RHR;
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// wait for byte be become available in rx holding register
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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return AT91C_BASE_SSC->SSC_RHR;
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}
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}
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}
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}
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//-----------------------------------------------------------------------------
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@ -83,11 +84,14 @@ static inline uint8_t rx_byte_from_fpga() {
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//
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// Note: The SSC receiver is never synchronized the calculation may be performed
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// on a i/q pair from two subsequent correlations, but does not matter.
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static inline int32_t sample_power() {
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int32_t q = (int8_t)rx_byte_from_fpga(); q = ABS(q);
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int32_t i = (int8_t)rx_byte_from_fpga(); i = ABS(i);
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static inline int32_t sample_power()
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{
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int32_t q = (int8_t)rx_byte_from_fpga();
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q = ABS(q);
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int32_t i = (int8_t)rx_byte_from_fpga();
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i = ABS(i);
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return MAX(i, q) + (MIN(i, q) >> 1);
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return MAX(i, q) + (MIN(i, q) >> 1);
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}
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// Returns a demedulated bit
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@ -97,14 +101,15 @@ static inline int32_t sample_power() {
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//
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// Note: The demodulator would be drifting (18.9us * 5 != 100us), rx_frame
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// has a delay loop that aligns rx_bit calls to the TAG tx timeslots.
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static inline bool rx_bit() {
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int32_t power;
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static inline bool rx_bit()
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{
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int32_t power;
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for (size_t i = 0; i<5; ++i) {
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power = sample_power();
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}
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for (size_t i = 0; i < 5; ++i) {
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power = sample_power();
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}
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return (power > INPUT_THRESHOLD);
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return (power > INPUT_THRESHOLD);
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}
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//-----------------------------------------------------------------------------
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@ -116,16 +121,17 @@ static inline bool rx_bit() {
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// be circumvented, but the adventage over bitbang would be little.
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//-----------------------------------------------------------------------------
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static inline void tx_bit(bool bit) {
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// insert pause
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LOW(GPIO_SSC_DOUT);
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last_frame_end += RWD_TIME_PAUSE;
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while (GET_TICKS < last_frame_end) { };
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HIGH(GPIO_SSC_DOUT);
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static inline void tx_bit(bool bit)
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{
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// insert pause
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LOW(GPIO_SSC_DOUT);
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last_frame_end += RWD_TIME_PAUSE;
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while (GET_TICKS < last_frame_end) { };
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HIGH(GPIO_SSC_DOUT);
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// return to high, wait for bit periode to end
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last_frame_end += (bit ? RWD_TIME_1 : RWD_TIME_0) - RWD_TIME_PAUSE;
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while (GET_TICKS < last_frame_end) { };
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// return to high, wait for bit periode to end
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last_frame_end += (bit ? RWD_TIME_1 : RWD_TIME_0) - RWD_TIME_PAUSE;
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while (GET_TICKS < last_frame_end) { };
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}
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//-----------------------------------------------------------------------------
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@ -138,163 +144,168 @@ static inline void tx_bit(bool bit) {
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// present.
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//-----------------------------------------------------------------------------
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static void tx_frame(uint32_t frame, uint8_t len) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
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static void tx_frame(uint32_t frame, uint8_t len)
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{
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
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// wait for next tx timeslot
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last_frame_end += RWD_FRAME_WAIT;
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while (GET_TICKS < last_frame_end) { };
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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// transmit frame, MSB first
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for (uint8_t i = 0; i < len; ++i) {
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bool bit = (frame >> i) & 0x01;
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tx_bit(bit ^ legic_prng_get_bit());
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legic_prng_forward(1);
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};
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// add pause to mark end of the frame
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LOW(GPIO_SSC_DOUT);
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last_frame_end += RWD_TIME_PAUSE;
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while (GET_TICKS < last_frame_end) { };
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HIGH(GPIO_SSC_DOUT);
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// log
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uint8_t cmdbytes[] = {len, BYTEx(frame, 0), BYTEx(frame, 1), BYTEx(frame, 2)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, true);
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}
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static uint32_t rx_frame(uint8_t len) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
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| FPGA_HF_READER_RX_XCORR_848_KHZ
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| FPGA_HF_READER_RX_XCORR_QUARTER);
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// hold sampling until card is expected to respond
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last_frame_end += TAG_FRAME_WAIT;
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while (GET_TICKS < last_frame_end) { };
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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uint32_t frame = 0;
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for (uint8_t i = 0; i < len; ++i) {
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frame |= (rx_bit() ^ legic_prng_get_bit()) << i;
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legic_prng_forward(1);
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// rx_bit runs only 95us, resync to TAG_BIT_PERIOD
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last_frame_end += TAG_BIT_PERIOD;
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while (GET_TICKS < last_frame_end) { };
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}
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// log
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uint8_t cmdbytes[] = {len, BYTEx(frame, 0), BYTEx(frame, 1)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, false);
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return frame;
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}
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static bool rx_ack() {
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// change fpga into rx mode
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
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| FPGA_HF_READER_RX_XCORR_848_KHZ
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| FPGA_HF_READER_RX_XCORR_QUARTER);
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// hold sampling until card is expected to respond
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last_frame_end += TAG_FRAME_WAIT;
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while (GET_TICKS < last_frame_end) { };
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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uint32_t ack = 0;
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for (uint8_t i = 0; i < TAG_WRITE_TIMEOUT; ++i) {
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// sample bit
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ack = rx_bit();
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legic_prng_forward(1);
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// rx_bit runs only 95us, resync to TAG_BIT_PERIOD
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last_frame_end += TAG_BIT_PERIOD;
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// wait for next tx timeslot
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last_frame_end += RWD_FRAME_WAIT;
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while (GET_TICKS < last_frame_end) { };
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// check if it was an ACK
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if (ack) {
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break;
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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// transmit frame, MSB first
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for (uint8_t i = 0; i < len; ++i) {
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bool bit = (frame >> i) & 0x01;
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tx_bit(bit ^ legic_prng_get_bit());
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legic_prng_forward(1);
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};
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// add pause to mark end of the frame
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LOW(GPIO_SSC_DOUT);
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last_frame_end += RWD_TIME_PAUSE;
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while (GET_TICKS < last_frame_end) { };
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HIGH(GPIO_SSC_DOUT);
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// log
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uint8_t cmdbytes[] = {len, BYTEx(frame, 0), BYTEx(frame, 1), BYTEx(frame, 2)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, true);
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}
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static uint32_t rx_frame(uint8_t len)
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{
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
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| FPGA_HF_READER_RX_XCORR_848_KHZ
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| FPGA_HF_READER_RX_XCORR_QUARTER);
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// hold sampling until card is expected to respond
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last_frame_end += TAG_FRAME_WAIT;
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while (GET_TICKS < last_frame_end) { };
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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uint32_t frame = 0;
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for (uint8_t i = 0; i < len; ++i) {
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frame |= (rx_bit() ^ legic_prng_get_bit()) << i;
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legic_prng_forward(1);
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// rx_bit runs only 95us, resync to TAG_BIT_PERIOD
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last_frame_end += TAG_BIT_PERIOD;
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while (GET_TICKS < last_frame_end) { };
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}
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}
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// log
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uint8_t cmdbytes[] = {1, BYTEx(ack, 0)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, false);
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// log
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uint8_t cmdbytes[] = {len, BYTEx(frame, 0), BYTEx(frame, 1)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, false);
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return ack;
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return frame;
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}
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static bool rx_ack()
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{
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// change fpga into rx mode
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
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| FPGA_HF_READER_RX_XCORR_848_KHZ
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| FPGA_HF_READER_RX_XCORR_QUARTER);
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// hold sampling until card is expected to respond
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last_frame_end += TAG_FRAME_WAIT;
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while (GET_TICKS < last_frame_end) { };
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// backup ts for trace log
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uint32_t last_frame_start = last_frame_end;
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uint32_t ack = 0;
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for (uint8_t i = 0; i < TAG_WRITE_TIMEOUT; ++i) {
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// sample bit
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ack = rx_bit();
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legic_prng_forward(1);
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// rx_bit runs only 95us, resync to TAG_BIT_PERIOD
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last_frame_end += TAG_BIT_PERIOD;
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while (GET_TICKS < last_frame_end) { };
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// check if it was an ACK
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if (ack) {
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break;
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}
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}
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// log
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uint8_t cmdbytes[] = {1, BYTEx(ack, 0)};
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LogTrace(cmdbytes, sizeof(cmdbytes), last_frame_start, last_frame_end, NULL, false);
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return ack;
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}
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//-----------------------------------------------------------------------------
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// Legic Reader
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//-----------------------------------------------------------------------------
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static int init_card(uint8_t cardtype, legic_card_select_t *p_card) {
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p_card->tagtype = cardtype;
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static int init_card(uint8_t cardtype, legic_card_select_t *p_card)
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{
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p_card->tagtype = cardtype;
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switch(p_card->tagtype) {
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case 0x0d:
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p_card->cmdsize = 6;
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p_card->addrsize = 5;
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p_card->cardsize = 22;
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break;
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case 0x1d:
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p_card->cmdsize = 9;
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p_card->addrsize = 8;
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p_card->cardsize = 256;
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break;
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case 0x3d:
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p_card->cmdsize = 11;
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p_card->addrsize = 10;
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p_card->cardsize = 1024;
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break;
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default:
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p_card->cmdsize = 0;
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p_card->addrsize = 0;
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p_card->cardsize = 0;
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return 2;
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}
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return 0;
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switch (p_card->tagtype) {
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case 0x0d:
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p_card->cmdsize = 6;
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p_card->addrsize = 5;
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p_card->cardsize = 22;
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break;
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case 0x1d:
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p_card->cmdsize = 9;
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p_card->addrsize = 8;
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p_card->cardsize = 256;
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break;
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case 0x3d:
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p_card->cmdsize = 11;
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p_card->addrsize = 10;
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p_card->cardsize = 1024;
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break;
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default:
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p_card->cmdsize = 0;
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p_card->addrsize = 0;
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p_card->cardsize = 0;
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return 2;
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}
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return 0;
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}
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static void init_reader(bool clear_mem) {
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// configure FPGA
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
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| FPGA_HF_READER_RX_XCORR_848_KHZ
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| FPGA_HF_READER_RX_XCORR_QUARTER);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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LED_A_ON();
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static void init_reader(bool clear_mem)
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{
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// configure FPGA
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
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| FPGA_HF_READER_RX_XCORR_848_KHZ
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| FPGA_HF_READER_RX_XCORR_QUARTER);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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LED_A_ON();
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// configure SSC with defaults
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FpgaSetupSsc();
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// configure SSC with defaults
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FpgaSetupSsc();
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// re-claim GPIO_SSC_DOUT as GPIO and enable output
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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HIGH(GPIO_SSC_DOUT);
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// re-claim GPIO_SSC_DOUT as GPIO and enable output
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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HIGH(GPIO_SSC_DOUT);
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// reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
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legic_mem = BigBuf_get_EM_addr();
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if (legic_mem) {
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memset(legic_mem, 0x00, LEGIC_CARD_MEMSIZE);
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}
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// reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
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legic_mem = BigBuf_get_EM_addr();
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if (legic_mem) {
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memset(legic_mem, 0x00, LEGIC_CARD_MEMSIZE);
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}
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// start trace
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clear_trace();
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set_tracing(true);
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// start trace
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clear_trace();
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set_tracing(true);
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// init crc calculator
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crc_init(&legic_crc, 4, 0x19 >> 1, 0x05, 0);
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// init crc calculator
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crc_init(&legic_crc, 4, 0x19 >> 1, 0x05, 0);
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// start us timer
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StartTicks();
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// start us timer
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StartTicks();
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}
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// Setup reader to card connection
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@ -303,89 +314,93 @@ static void init_reader(bool clear_mem) {
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// - Transmit initialisation vector 7 bits
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// - Receive card type 6 bits
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// - Transmit Acknowledge 6 bits
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static uint32_t setup_phase(uint8_t iv) {
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// init coordination timestamp
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last_frame_end = GET_TICKS;
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static uint32_t setup_phase(uint8_t iv)
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{
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// init coordination timestamp
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last_frame_end = GET_TICKS;
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// Switch on carrier and let the card charge for 5ms.
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last_frame_end += 7500;
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while (GET_TICKS < last_frame_end) { };
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// Switch on carrier and let the card charge for 5ms.
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last_frame_end += 7500;
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while (GET_TICKS < last_frame_end) { };
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legic_prng_init(0);
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tx_frame(iv, 7);
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legic_prng_init(0);
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tx_frame(iv, 7);
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// configure prng
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legic_prng_init(iv);
|
||||
legic_prng_forward(2);
|
||||
// configure prng
|
||||
legic_prng_init(iv);
|
||||
legic_prng_forward(2);
|
||||
|
||||
// receive card type
|
||||
int32_t card_type = rx_frame(6);
|
||||
legic_prng_forward(3);
|
||||
// receive card type
|
||||
int32_t card_type = rx_frame(6);
|
||||
legic_prng_forward(3);
|
||||
|
||||
// send obsfuscated acknowledgment frame
|
||||
switch (card_type) {
|
||||
case 0x0D:
|
||||
tx_frame(0x19, 6); // MIM22 | READCMD = 0x18 | 0x01
|
||||
break;
|
||||
case 0x1D:
|
||||
case 0x3D:
|
||||
tx_frame(0x39, 6); // MIM256 | READCMD = 0x38 | 0x01
|
||||
break;
|
||||
}
|
||||
// send obsfuscated acknowledgment frame
|
||||
switch (card_type) {
|
||||
case 0x0D:
|
||||
tx_frame(0x19, 6); // MIM22 | READCMD = 0x18 | 0x01
|
||||
break;
|
||||
case 0x1D:
|
||||
case 0x3D:
|
||||
tx_frame(0x39, 6); // MIM256 | READCMD = 0x38 | 0x01
|
||||
break;
|
||||
}
|
||||
|
||||
return card_type;
|
||||
return card_type;
|
||||
}
|
||||
|
||||
static uint8_t calc_crc4(uint16_t cmd, uint8_t cmd_sz, uint8_t value) {
|
||||
crc_clear(&legic_crc);
|
||||
crc_update(&legic_crc, (value << cmd_sz) | cmd, 8 + cmd_sz);
|
||||
return crc_finish(&legic_crc);
|
||||
static uint8_t calc_crc4(uint16_t cmd, uint8_t cmd_sz, uint8_t value)
|
||||
{
|
||||
crc_clear(&legic_crc);
|
||||
crc_update(&legic_crc, (value << cmd_sz) | cmd, 8 + cmd_sz);
|
||||
return crc_finish(&legic_crc);
|
||||
}
|
||||
|
||||
static int16_t read_byte(uint16_t index, uint8_t cmd_sz) {
|
||||
uint16_t cmd = (index << 1) | LEGIC_READ;
|
||||
static int16_t read_byte(uint16_t index, uint8_t cmd_sz)
|
||||
{
|
||||
uint16_t cmd = (index << 1) | LEGIC_READ;
|
||||
|
||||
// read one byte
|
||||
LED_B_ON();
|
||||
legic_prng_forward(2);
|
||||
tx_frame(cmd, cmd_sz);
|
||||
legic_prng_forward(2);
|
||||
uint32_t frame = rx_frame(12);
|
||||
LED_B_OFF();
|
||||
// read one byte
|
||||
LED_B_ON();
|
||||
legic_prng_forward(2);
|
||||
tx_frame(cmd, cmd_sz);
|
||||
legic_prng_forward(2);
|
||||
uint32_t frame = rx_frame(12);
|
||||
LED_B_OFF();
|
||||
|
||||
// split frame into data and crc
|
||||
uint8_t byte = BYTEx(frame, 0);
|
||||
uint8_t crc = BYTEx(frame, 1);
|
||||
// split frame into data and crc
|
||||
uint8_t byte = BYTEx(frame, 0);
|
||||
uint8_t crc = BYTEx(frame, 1);
|
||||
|
||||
// check received against calculated crc
|
||||
uint8_t calc_crc = calc_crc4(cmd, cmd_sz, byte);
|
||||
if (calc_crc != crc) {
|
||||
Dbprintf("!!! crc mismatch: %x != %x !!!", calc_crc, crc);
|
||||
return -1;
|
||||
}
|
||||
// check received against calculated crc
|
||||
uint8_t calc_crc = calc_crc4(cmd, cmd_sz, byte);
|
||||
if (calc_crc != crc) {
|
||||
Dbprintf("!!! crc mismatch: %x != %x !!!", calc_crc, crc);
|
||||
return -1;
|
||||
}
|
||||
|
||||
legic_prng_forward(1);
|
||||
legic_prng_forward(1);
|
||||
|
||||
return byte;
|
||||
return byte;
|
||||
}
|
||||
|
||||
// Transmit write command, wait until (3.6ms) the tag sends back an unencrypted
|
||||
// ACK ('1' bit) and forward the prng time based.
|
||||
bool write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
|
||||
uint32_t cmd = index << 1 | LEGIC_WRITE; // prepare command
|
||||
uint8_t crc = calc_crc4(cmd, addr_sz + 1, byte); // calculate crc
|
||||
cmd |= byte << (addr_sz + 1); // append value
|
||||
cmd |= (crc & 0xF) << (addr_sz + 1 + 8); // and crc
|
||||
bool write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz)
|
||||
{
|
||||
uint32_t cmd = index << 1 | LEGIC_WRITE; // prepare command
|
||||
uint8_t crc = calc_crc4(cmd, addr_sz + 1, byte); // calculate crc
|
||||
cmd |= byte << (addr_sz + 1); // append value
|
||||
cmd |= (crc & 0xF) << (addr_sz + 1 + 8); // and crc
|
||||
|
||||
// send write command
|
||||
LED_C_ON();
|
||||
legic_prng_forward(2);
|
||||
tx_frame(cmd, addr_sz + 1 + 8 + 4); // cmd_sz = addr_sz + cmd + data + crc
|
||||
legic_prng_forward(3);
|
||||
LED_C_OFF();
|
||||
// send write command
|
||||
LED_C_ON();
|
||||
legic_prng_forward(2);
|
||||
tx_frame(cmd, addr_sz + 1 + 8 + 4); // cmd_sz = addr_sz + cmd + data + crc
|
||||
legic_prng_forward(3);
|
||||
LED_C_OFF();
|
||||
|
||||
// wait for ack
|
||||
return rx_ack();
|
||||
// wait for ack
|
||||
return rx_ack();
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
|
|
@ -393,111 +408,114 @@ bool write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
|
|||
//
|
||||
// Only this functions are public / called from appmain.c
|
||||
//-----------------------------------------------------------------------------
|
||||
void LegicRfInfo(void) {
|
||||
// configure ARM and FPGA
|
||||
init_reader(false);
|
||||
void LegicRfInfo(void)
|
||||
{
|
||||
// configure ARM and FPGA
|
||||
init_reader(false);
|
||||
|
||||
// establish shared secret and detect card type
|
||||
uint8_t card_type = setup_phase(0x01);
|
||||
if (init_card(card_type, &card) != 0) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
|
||||
// read UID
|
||||
for (uint8_t i = 0; i < sizeof(card.uid); ++i) {
|
||||
int16_t byte = read_byte(i, card.cmdsize);
|
||||
if (byte == -1) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
// establish shared secret and detect card type
|
||||
uint8_t card_type = setup_phase(0x01);
|
||||
if (init_card(card_type, &card) != 0) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
card.uid[i] = byte & 0xFF;
|
||||
}
|
||||
|
||||
// read MCC and check against UID
|
||||
int16_t mcc = read_byte(4, card.cmdsize);
|
||||
int16_t calc_mcc = CRC8Legic(card.uid, 4);;
|
||||
if (mcc != calc_mcc) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
// read UID
|
||||
for (uint8_t i = 0; i < sizeof(card.uid); ++i) {
|
||||
int16_t byte = read_byte(i, card.cmdsize);
|
||||
if (byte == -1) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
card.uid[i] = byte & 0xFF;
|
||||
}
|
||||
|
||||
// OK
|
||||
cmd_send(CMD_ACK, 1, 0, 0, (uint8_t*)&card, sizeof(legic_card_select_t));
|
||||
// read MCC and check against UID
|
||||
int16_t mcc = read_byte(4, card.cmdsize);
|
||||
int16_t calc_mcc = CRC8Legic(card.uid, 4);;
|
||||
if (mcc != calc_mcc) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
|
||||
// OK
|
||||
cmd_send(CMD_ACK, 1, 0, 0, (uint8_t *)&card, sizeof(legic_card_select_t));
|
||||
|
||||
OUT:
|
||||
switch_off();
|
||||
StopTicks();
|
||||
switch_off();
|
||||
StopTicks();
|
||||
}
|
||||
|
||||
void LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
|
||||
// configure ARM and FPGA
|
||||
init_reader(false);
|
||||
void LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv)
|
||||
{
|
||||
// configure ARM and FPGA
|
||||
init_reader(false);
|
||||
|
||||
// establish shared secret and detect card type
|
||||
uint8_t card_type = setup_phase(iv);
|
||||
if (init_card(card_type, &card) != 0) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
|
||||
// do not read beyond card memory
|
||||
if (len + offset > card.cardsize) {
|
||||
len = card.cardsize - offset;
|
||||
}
|
||||
|
||||
for (uint16_t i = 0; i < len; ++i) {
|
||||
int16_t byte = read_byte(offset + i, card.cmdsize);
|
||||
if (byte == -1) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
// establish shared secret and detect card type
|
||||
uint8_t card_type = setup_phase(iv);
|
||||
if (init_card(card_type, &card) != 0) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
legic_mem[i] = byte;
|
||||
}
|
||||
|
||||
// OK
|
||||
cmd_send(CMD_ACK, 1, len, 0, legic_mem, len);
|
||||
// do not read beyond card memory
|
||||
if (len + offset > card.cardsize) {
|
||||
len = card.cardsize - offset;
|
||||
}
|
||||
|
||||
for (uint16_t i = 0; i < len; ++i) {
|
||||
int16_t byte = read_byte(offset + i, card.cmdsize);
|
||||
if (byte == -1) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
legic_mem[i] = byte;
|
||||
}
|
||||
|
||||
// OK
|
||||
cmd_send(CMD_ACK, 1, len, 0, legic_mem, len);
|
||||
|
||||
OUT:
|
||||
switch_off();
|
||||
StopTicks();
|
||||
switch_off();
|
||||
StopTicks();
|
||||
}
|
||||
|
||||
void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
|
||||
// configure ARM and FPGA
|
||||
init_reader(false);
|
||||
void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data)
|
||||
{
|
||||
// configure ARM and FPGA
|
||||
init_reader(false);
|
||||
|
||||
// uid is not writeable
|
||||
if (offset <= WRITE_LOWERLIMIT) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
|
||||
// establish shared secret and detect card type
|
||||
uint8_t card_type = setup_phase(iv);
|
||||
if (init_card(card_type, &card) != 0) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
|
||||
// do not write beyond card memory
|
||||
if (len + offset > card.cardsize) {
|
||||
len = card.cardsize - offset;
|
||||
}
|
||||
|
||||
// write in reverse order, only then is DCF (decremental field) writable
|
||||
while (len-- > 0 && !BUTTON_PRESS()) {
|
||||
if (!write_byte(len + offset, data[len], card.addrsize)) {
|
||||
Dbprintf("operation failed | %02X | %02X | %02X", len + offset, len, data[len]);
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
// uid is not writeable
|
||||
if (offset <= WRITE_LOWERLIMIT) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
}
|
||||
|
||||
// OK
|
||||
cmd_send(CMD_ACK, 1, len, 0, legic_mem, len);
|
||||
// establish shared secret and detect card type
|
||||
uint8_t card_type = setup_phase(iv);
|
||||
if (init_card(card_type, &card) != 0) {
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
|
||||
// do not write beyond card memory
|
||||
if (len + offset > card.cardsize) {
|
||||
len = card.cardsize - offset;
|
||||
}
|
||||
|
||||
// write in reverse order, only then is DCF (decremental field) writable
|
||||
while (len-- > 0 && !BUTTON_PRESS()) {
|
||||
if (!write_byte(len + offset, data[len], card.addrsize)) {
|
||||
Dbprintf("operation failed | %02X | %02X | %02X", len + offset, len, data[len]);
|
||||
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
||||
goto OUT;
|
||||
}
|
||||
}
|
||||
|
||||
// OK
|
||||
cmd_send(CMD_ACK, 1, len, 0, legic_mem, len);
|
||||
|
||||
OUT:
|
||||
switch_off();
|
||||
StopTicks();
|
||||
switch_off();
|
||||
StopTicks();
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue